v_size = (req->dst.v_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;\r
req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) | ((uv_size) << PAGE_SHIFT);\r
req->dst.v_addr = (req->dst.v_addr & (~PAGE_MASK)) | ((v_size) << PAGE_SHIFT);\r
+\r
+ if (((req->alpha_rop_flag & 1) == 1) && (req->bitblt_mode == 0)) {\r
+ req->mmu_info.src1_base_addr = req->mmu_info.dst_base_addr;\r
+ req->mmu_info.src1_mmu_flag = req->mmu_info.dst_mmu_flag;\r
+ }\r
}\r
\r
/* flush data to DDR */\r
req->bitblt_mode = req_rga->bsfilter_flag;\r
\r
req->src_a_global_val = req_rga->alpha_global_value;\r
- req->dst_a_global_val = 0;\r
+ req->dst_a_global_val = req_rga->alpha_global_value;\r
req->rop_code = req_rga->rop_code;\r
req->rop_mode = 0;\r
\r
req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6); // dst_dither_down\r
req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7); // gradient fill mode sel\r
\r
- if(((req_rga->alpha_rop_flag) & 1)) {\r
- if((req_rga->alpha_rop_flag >> 3) & 1) {\r
+ if (((req_rga->alpha_rop_flag) & 1)) {\r
+ if ((req_rga->alpha_rop_flag >> 3) & 1) {\r
/* porter duff alpha enable */\r
- switch(req_rga->PD_mode)\r
+ switch (req_rga->PD_mode)\r
{\r
case 0: //dst = 0\r
break;\r
break;\r
case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;\r
break;\r
+ case 12:\r
+ req->alpha_mode_0 = 0x0010;\r
+ req->alpha_mode_1 = 0x0820;\r
+ break;\r
default:\r
break;\r
}\r
req->rop_mask_addr = req_rga->rop_mask_addr;\r
req->bitblt_mode = req_rga->bsfilter_flag;\r
req->src_a_global_val = req_rga->alpha_global_value;\r
- req->dst_a_global_val = 0;\r
+ req->dst_a_global_val = req_rga->alpha_global_value;\r
req->rop_code = req_rga->rop_code;\r
req->rop_mode = 0;\r
req->color_fill_mode = req_rga->color_fill_mode;\r
break;\r
case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;\r
break;\r
+ case 12:\r
+ req->alpha_mode_0 = 0x0010;\r
+ req->alpha_mode_1 = 0x0820;\r
+ break;\r
default:\r
break;\r
}\r