Minor debug output tweak.
authorEvan Cheng <evan.cheng@apple.com>
Fri, 9 Jan 2009 20:42:34 +0000 (20:42 +0000)
committerEvan Cheng <evan.cheng@apple.com>
Fri, 9 Jan 2009 20:42:34 +0000 (20:42 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62005 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

index 9fee4b7aae3c50beba84d0259f83f02c5f604524..65de7a5c8f8263a0d8b10df5fa45f952c014f056 100644 (file)
@@ -726,7 +726,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
           }
           SmallVector<SUnit*, 2> Copies;
           InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
-          DOUT << "Adding an edge from SU # " << TrySU->NodeNum
+          DOUT << "Adding an edge from SU #" << TrySU->NodeNum
                << " to SU #" << Copies.front()->NodeNum << "\n";
           AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
                               /*Reg=*/0, /*isNormalMemory=*/false,
@@ -735,7 +735,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
           NewDef = Copies.back();
         }
 
-        DOUT << "Adding an edge from SU # " << NewDef->NodeNum
+        DOUT << "Adding an edge from SU #" << NewDef->NodeNum
              << " to SU #" << TrySU->NodeNum << "\n";
         LiveRegDefs[Reg] = NewDef;
         AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,