Remove dead code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23179 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 915b9d0a61b4d19c4286d6c9000afee64e4757ea..9a978295b84ff9d3f40d1db194815a0fb1be7bee 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1220,44 +1220,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     CurDAG->ReplaceAllUsesWith(N, Result);
     return Result[Op.ResNo];
   }
-  case ISD::SHL_PARTS: {
-    SDOperand LO = Select(N->getOperand(0));
-    SDOperand HI = Select(N->getOperand(1));
-    SDOperand SH = Select(N->getOperand(2));
-    SDOperand SH_LO_R = CurDAG->getTargetNode(PPC::SUBFIC, MVT::i32, MVT::Flag,
-                                              SH, getI32Imm(32));
-    SDOperand SH_LO_L = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, SH, 
-                                          getI32Imm((unsigned)-32));
-    SDOperand HI_SHL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, HI, SH);
-    SDOperand HI_LOR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, LO, SH_LO_R);
-    SDOperand HI_LOL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, LO, SH_LO_L);
-    SDOperand HI_OR =  CurDAG->getTargetNode(PPC::OR, MVT::i32, HI_SHL, HI_LOR);
-
-    std::vector<SDOperand> Result;
-    Result.push_back(CurDAG->getTargetNode(PPC::SLW, MVT::i32, LO, SH));
-    Result.push_back(CurDAG->getTargetNode(PPC::OR, MVT::i32, HI_OR, HI_LOL));
-    CurDAG->ReplaceAllUsesWith(N, Result);
-    return Result[Op.ResNo];
-  }
-  case ISD::SRL_PARTS: {
-    SDOperand LO = Select(N->getOperand(0));
-    SDOperand HI = Select(N->getOperand(1));
-    SDOperand SH = Select(N->getOperand(2));
-    SDOperand SH_HI_L = CurDAG->getTargetNode(PPC::SUBFIC, MVT::i32, MVT::Flag,
-                                              SH, getI32Imm(32));
-    SDOperand SH_HI_R = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, SH, 
-                                              getI32Imm((unsigned)-32));
-    SDOperand LO_SHR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, LO, SH);
-    SDOperand LO_HIL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, HI, SH_HI_L);
-    SDOperand LO_HIR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, HI, SH_HI_R);
-    SDOperand LO_OR =  CurDAG->getTargetNode(PPC::OR, MVT::i32, LO_SHR, LO_HIL);
-
-    std::vector<SDOperand> Result;
-    Result.push_back(CurDAG->getTargetNode(PPC::OR, MVT::i32, LO_OR, LO_HIR));
-    Result.push_back(CurDAG->getTargetNode(PPC::SRW, MVT::i32, HI, SH));
-    CurDAG->ReplaceAllUsesWith(N, Result);
-    return Result[Op.ResNo];
-  }
     
   case ISD::LOAD:
   case ISD::EXTLOAD:

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 9b5a564a29efb03a05551a3112b06ae2f9a52c10..eba1419f43b9de2534b7a7be763e7fdf9b3cbac2 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -801,8 +801,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     break;
   case ISD::ADD_PARTS:
   case ISD::SUB_PARTS:
-  case ISD::SHL_PARTS:
-  case ISD::SRL_PARTS:
     Result = MakeReg(Node->getValueType(0));
     ExprMap[N.getValue(0)] = Result;
     for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
@@ -1438,41 +1436,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     return Result+N.ResNo;
   }
 
-  case ISD::SHL_PARTS:
-  case ISD::SRL_PARTS: {
-    assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
-           "Not an i64 shift!");
-    unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
-    unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
-    unsigned SHReg = FoldIfWideZeroExtend(N.getOperand(2));
-    Tmp1 = MakeIntReg();
-    Tmp2 = MakeIntReg();
-    Tmp3 = MakeIntReg();
-    unsigned Tmp4 = MakeIntReg();
-    unsigned Tmp5 = MakeIntReg();
-    unsigned Tmp6 = MakeIntReg();
-    BuildMI(BB, PPC::SUBFIC, 2, Tmp1).addReg(SHReg).addSImm(32);
-    if (ISD::SHL_PARTS == opcode) {
-      BuildMI(BB, PPC::SLW, 2, Tmp2).addReg(ShiftOpHi).addReg(SHReg);
-      BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1);
-      BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
-      BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
-      BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpLo).addReg(Tmp5);
-      BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6);
-      BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg);
-    } else {
-      assert (opcode == ISD::SRL_PARTS);
-      BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
-      BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
-      BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
-      BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
-      BuildMI(BB, PPC::SRW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
-      BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp4).addReg(Tmp6);
-      BuildMI(BB, PPC::SRW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
-    }
-    return Result+N.ResNo;
-  }
-
   case ISD::FP_TO_SINT: {
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = MakeFPReg();