R600: Rewrite an awkward loop in R600MachineScheduler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183458 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/lib/Target/R600/R600OptimizeVectorRegisters.cpp
index 7c4aee76dda02cb487f5ffe4276e9c69788bd4d7..b122baef1240948cc9201f7ef80b12e1d60e3293 100644 (file)
--- a/lib/Target/R600/R600OptimizeVectorRegisters.cpp
+++ b/lib/Target/R600/R600OptimizeVectorRegisters.cpp
@@ -159,6 +159,19 @@ bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
   return true;
 }
 
+static
+unsigned getReassignedChan(
+    const std::vector<std::pair<unsigned, unsigned> > &RemapChan,
+    unsigned Chan) {
+  for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
+    if (RemapChan[j].first == Chan) {
+      return RemapChan[j].second;
+      break;
+    }
+  }
+  llvm_unreachable("Chan wasn't reassigned");
+}
+
 MachineInstr *R600VectorRegMerger::RebuildVector(
     RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
     const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const {
@@ -179,13 +192,8 @@ MachineInstr *R600VectorRegMerger::RebuildVector(
     unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
     unsigned SubReg = (*It).first;
     unsigned Swizzle = (*It).second;
-    unsigned Chan = 0xDEADBEEF;
-    for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
-      if (RemapChan[j].first == Swizzle) {
-        Chan = RemapChan[j].second;
-        break;
-      }
-    }
+    unsigned Chan = getReassignedChan(RemapChan, Swizzle);
+
     MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
         DstReg)
         .addReg(SrcVec)