Encoding for ARM LDRSB instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 251e5c27a0b73f1bf5f509af9da6c7a97a74038e..5f603f6d0dc3f60807c3071efa460d16e1ee4f89 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -700,14 +700,19 @@ class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
       opc, asm, "", pattern> {
-  let Inst{4}     = 1;
-  let Inst{5}     = 0; // H bit
-  let Inst{6}     = 1; // S bit
-  let Inst{7}     = 1;
-  let Inst{20}    = 1; // L bit
-  let Inst{21}    = 0; // W bit
-  let Inst{24}    = 1; // P bit
+  bits<14> addr;
+  bits<4> Rt;
   let Inst{27-25} = 0b000;
+  let Inst{24}    = 1; // P bit
+  let Inst{23}    = addr{8};      // U bit
+  let Inst{22}    = addr{13};     // 1 == imm8, 0 == Rm
+  let Inst{21}    = 0; // W bit
+  let Inst{20}    = 1; // L bit
+  let Inst{19-16} = addr{12-9};   // Rn
+  let Inst{15-12} = Rt;           // Rt
+  let Inst{11-8}  = addr{7-4};    // imm7_4/zero
+  let Inst{7-4}   = 0b1101;
+  let Inst{3-0}   = addr{3-0};    // imm3_0/Rm
 }
 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
                string asm, list<dag> pattern>