--- /dev/null
+ARM Marvell SoCs
+================
+
+This document lists all the ARM Marvell SoCs that are currently
+supported in mainline by the Linux kernel. As the Marvell families of
+SoCs are large and complex, it is hard to understand where the support
+for a particular SoC is available in the Linux kernel. This document
+tries to help in understanding where those SoCs are supported, and to
+match them with their corresponding public datasheet, when available.
+
+Orion family
+------------
+
+ Flavors:
+ 88F5082
+ 88F5181
+ 88F5181L
+ 88F5182
+ Datasheet : http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
+ Programmer's User Guide : http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensource-manual.pdf
+ User Manual : http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
+ 88F5281
+ Datasheet : http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sheet.pdf
+ 88F6183
+ Core: Feroceon ARMv5 compatible
+ Linux kernel mach directory: arch/arm/mach-orion5x
+ Linux kernel plat directory: arch/arm/plat-orion
+
+Kirkwood family
+---------------
+
+ Flavors:
+ 88F6282 a.k.a Armada 300
+ Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
+ 88F6283 a.k.a Armada 310
+ Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
+ 88F6190
+ Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6190-003_WEB.pdf
+ Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
+ Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+ 88F6192
+ Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6192-003_ver1.pdf
+ Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
+ Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+ 88F6182
+ 88F6180
+ Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6180-003_ver1.pdf
+ Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf
+ Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+ 88F6281
+ Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf
+ Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
+ Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+ Homepage: http://www.marvell.com/embedded-processors/kirkwood/
+ Core: Feroceon ARMv5 compatible
+ Linux kernel mach directory: arch/arm/mach-kirkwood
+ Linux kernel plat directory: arch/arm/plat-orion
+
+Discovery family
+----------------
+
+ Flavors:
+ MV78100
+ Product Brief : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78100-003_WEB.pdf
+ Hardware Spec : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78100_OpenSource.pdf
+ Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
+ MV78200
+ Product Brief : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78200-002_WEB.pdf
+ Hardware Spec : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78200_OpenSource.pdf
+ Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
+ MV76100
+ Not supported by the Linux kernel.
+
+ Core: Feroceon ARMv5 compatible
+
+ Linux kernel mach directory: arch/arm/mach-mv78xx0
+ Linux kernel plat directory: arch/arm/plat-orion
+
+EBU Armada family
+-----------------
+
+ Armada 370 Flavors:
+ 88F6710
+ 88F6707
+ 88F6W11
+
+ Armada XP Flavors:
+ MV78230
+ MV78260
+ MV78460
+
+ Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
+ No public datasheet available.
+
+ Core: Sheeva ARMv7 compatible
+
+ Linux kernel mach directory: arch/arm/mach-mvebu
+ Linux kernel plat directory: none
+
+Avanta family
+-------------
+
+ Flavors:
+ 88F6510
+ 88F6530P
+ 88F6550
+ 88F6560
+ Homepage : http://www.marvell.com/broadband/
+ Product Brief: http://www.marvell.com/broadband/assets/Marvell_Avanta_88F6510_305_060-001_product_brief.pdf
+ No public datasheet available.
+
+ Core: ARMv5 compatible
+
+ Linux kernel mach directory: no code in mainline yet, planned for the future
+ Linux kernel plat directory: no code in mainline yet, planned for the future
+
+Dove family (application processor)
+-----------------------------------
+
+ Flavors:
+ 88AP510 a.k.a Armada 510
+ Product Brief : http://www.marvell.com/application-processors/armada-500/assets/Marvell_Armada510_SoC.pdf
+ Hardware Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Hardware-Spec.pdf
+ Functional Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf
+ Homepage: http://www.marvell.com/application-processors/armada-500/
+ Core: ARMv7 compatible
+ Directory: arch/arm/mach-dove
+
+PXA 2xx/3xx/93x/95x family
+--------------------------
+
+ Flavors:
+ PXA21x, PXA25x, PXA26x
+ Application processor only
+ Core: ARMv5 XScale core
+ PXA270, PXA271, PXA272
+ Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_pb.pdf
+ Design guide : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_design_guide.pdf
+ Developers manual : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_dev_man.pdf
+ Specification : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_emts.pdf
+ Specification update : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf
+ Application processor only
+ Core: ARMv5 XScale core
+ PXA300, PXA310, PXA320
+ PXA 300 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA300_PB_R4.pdf
+ PXA 310 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA310_PB_R4.pdf
+ PXA 320 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA320_PB_R4.pdf
+ Design guide : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Design_Guide.pdf
+ Developers manual : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Developers_Manual.zip
+ Specifications : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_EMTS.pdf
+ Specification Update : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Spec_Update.zip
+ Reference Manual : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_TavorP_BootROM_Ref_Manual.pdf
+ Application processor only
+ Core: ARMv5 XScale core
+ PXA930, PXA935
+ Application processor with Communication processor
+ Core: ARMv5 XScale core
+ PXA955
+ Application processor with Communication processor
+ Core: ARMv7 compatible Sheeva PJ4 core
+
+ Comments:
+
+ * This line of SoCs originates from the XScale family developed by
+ Intel and acquired by Marvell in ~2006. The PXA21x, PXA25x,
+ PXA26x, PXA27x, PXA3xx and PXA93x were developed by Intel, while
+ the later PXA95x were developed by Marvell.
+
+ * Due to their XScale origin, these SoCs have virtually nothing in
+ common with the other (Kirkwood, Dove, etc.) families of Marvell
+ SoCs, except with the MMP/MMP2 family of SoCs.
+
+ Linux kernel mach directory: arch/arm/mach-pxa
+ Linux kernel plat directory: arch/arm/plat-pxa
+
+MMP/MMP2 family (communication processor)
+-----------------------------------------
+
+ Flavors:
+ PXA168, a.k.a Armada 168
+ Homepage : http://www.marvell.com/application-processors/armada-100/armada-168.jsp
+ Product brief : http://www.marvell.com/application-processors/armada-100/assets/pxa_168_pb.pdf
+ Hardware manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_datasheet.pdf
+ Software manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_software_manual.pdf
+ Specification update : http://www.marvell.com/application-processors/armada-100/assets/ARMADA16x_Spec_update.pdf
+ Boot ROM manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_ref_manual.pdf
+ App node package : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_app_note_package.pdf
+ Application processor only
+ Core: ARMv5 compatible Marvell PJ1 (Mohawk)
+ PXA910
+ Homepage : http://www.marvell.com/communication-processors/pxa910/
+ Product Brief : http://www.marvell.com/communication-processors/pxa910/assets/Marvell_PXA910_Platform-001_PB_final.pdf
+ Application processor with Communication processor
+ Core: ARMv5 compatible Marvell PJ1 (Mohawk)
+ MMP2, a.k.a Armada 610
+ Product Brief : http://www.marvell.com/application-processors/armada-600/assets/armada610_pb.pdf
+ Application processor only
+ Core: ARMv7 compatible Sheeva PJ4 core
+
+ Comments:
+
+ * This line of SoCs originates from the XScale family developed by
+ Intel and acquired by Marvell in ~2006. All the processors of
+ this MMP/MMP2 family were developed by Marvell.
+
+ * Due to their XScale origin, these SoCs have virtually nothing in
+ common with the other (Kirkwood, Dove, etc.) families of Marvell
+ SoCs, except with the PXA family of SoCs listed above.
+
+ Linux kernel mach directory: arch/arm/mach-mmp
+ Linux kernel plat directory: arch/arm/plat-pxa
+
+Long-term plans
+---------------
+
+ * Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ and
+ mach-kirkwood/ into the mach-mvebu/ to support all SoCs from the
+ Marvell EBU (Engineering Business Unit) in a single mach-<foo>
+ directory. The plat-orion/ would therefore disappear.
+
+ * Unify the mach-mmp/ and mach-pxa/ into the same mach-pxa
+ directory. The plat-pxa/ would therefore disappear.
+
+Credits
+-------
+
+ Maen Suleiman <maen@marvell.com>
+ Lior Amsalem <alior@marvell.com>
+ Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ Andrew Lunn <andrew@lunn.ch>
+ Nicolas Pitre <nico@fluxnic.net>
+ Eric Miao <eric.y.miao@gmail.com>
config ARCH_DOVE
bool "Marvell Dove"
select CPU_V7
- select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
+ select MIGHT_HAVE_PCI
select PLAT_ORION
+ select USB_ARCH_HAS_EHCI
help
Support for the Marvell Dove SoC 88AP510
--- /dev/null
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+ model = "Compulab CM-A510";
+ compatible = "compulab,cm-a510", "marvell,dove";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+ status = "okay";
+
+ /* spi0.0: 4M Flash Winbond W25Q32BV */
+ spi-flash@0 {
+ compatible = "st,w25q32";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
--- /dev/null
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+ model = "SolidRun CuBox";
+ compatible = "solidrun,cubox", "marvell,dove";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ power {
+ label = "Power";
+ gpios = <&gpio0 18 1>;
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+ status = "okay";
+
+ /* spi0.0: 4M Flash Winbond W25Q32BV */
+ spi-flash@0 {
+ compatible = "st,w25q32";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+ model = "Marvell DB-MV88AP510-BP Development Board";
+ compatible = "marvell,dove-db", "marvell,dove";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+ status = "okay";
+
+ /* spi0.0: 4M Flash ST-M25P32-VMF6P */
+ spi-flash@0 {
+ compatible = "st,m25p32";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
--- /dev/null
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "marvell,dove";
+ model = "Marvell Armada 88AP510 SoC";
+
+ interrupt-parent = <&intc>;
+
+ intc: interrupt-controller {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xf1020204 0x04>,
+ <0xf1020214 0x04>;
+ };
+
+ mbus@f1000000 {
+ compatible = "simple-bus";
+ ranges = <0 0xf1000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@12000 {
+ compatible = "ns16550a";
+ reg = <0x12000 0x100>;
+ reg-shift = <2>;
+ interrupts = <7>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ uart1: serial@12100 {
+ compatible = "ns16550a";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <8>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ uart2: serial@12200 {
+ compatible = "ns16550a";
+ reg = <0x12000 0x100>;
+ reg-shift = <2>;
+ interrupts = <9>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ uart3: serial@12300 {
+ compatible = "ns16550a";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clock-frequency = <166666667>;
+ status = "disabled";
+ };
+
+ wdt: wdt@20300 {
+ compatible = "marvell,orion-wdt";
+ reg = <0x20300 0x28>;
+ };
+
+ gpio0: gpio@d0400 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0xd0400 0x20>;
+ ngpio = <32>;
+ interrupts = <12>, <13>, <14>, <60>;
+ };
+
+ gpio1: gpio@d0420 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0xd0420 0x20>;
+ ngpio = <32>;
+ interrupts = <61>;
+ };
+
+ gpio2: gpio@e8400 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0xe8400 0x0c>;
+ ngpio = <8>;
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,orion-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <6>;
+ reg = <0x10600 0x28>;
+ status = "disabled";
+ };
+
+ spi1: spi@14600 {
+ compatible = "marvell,orion-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ interrupts = <5>;
+ reg = <0x14600 0x28>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11000 {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <11>;
+ clock-frequency = <400000>;
+ timeout-ms = <1000>;
+ status = "disabled";
+ };
+
+ sdio0: sdio@92000 {
+ compatible = "marvell,dove-sdhci";
+ reg = <0x92000 0x100>;
+ interrupts = <35>, <37>;
+ status = "disabled";
+ };
+
+ sdio1: sdio@90000 {
+ compatible = "marvell,dove-sdhci";
+ reg = <0x90000 0x100>;
+ interrupts = <36>, <38>;
+ status = "disabled";
+ };
+
+ sata0: sata@a0000 {
+ compatible = "marvell,orion-sata";
+ reg = <0xa0000 0x2400>;
+ interrupts = <62>;
+ nr-ports = <1>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+ model = "Seagate FreeAgent Dockstar";
+ compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+ };
+
+ ocp@f1000000 {
+ serial@12000 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ nand@3000000 {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "data";
+ reg = <0x0500000 0xfb00000>;
+ };
+ };
+ };
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ health {
+ label = "status:green:health";
+ gpios = <&gpio1 14 1>;
+ linux,default-trigger = "default-on";
+ };
+ fault {
+ label = "status:orange:fault";
+ gpios = <&gpio1 15 1>;
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+ model = "Iomega StorCenter ix2-200";
+ compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+
+ ocp@f1000000 {
+ i2c@11000 {
+ status = "okay";
+
+ lm63: lm63@4c {
+ compatible = "national,lm63";
+ reg = <0x4c>;
+ };
+ };
+
+ serial@12000 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ nand@3000000 {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0xa0000 0x20000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x100000 0x300000>;
+ };
+
+ partition@400000 {
+ label = "uInitrd";
+ reg = <0x540000 0x1000000>;
+ };
+ };
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+
+ };
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ power_led {
+ label = "status:white:power_led";
+ gpios = <&gpio0 16 0>;
+ linux,default-trigger = "default-on";
+ };
+ health_led1 {
+ label = "status:red:health_led";
+ gpios = <&gpio1 5 0>;
+ };
+ health_led2 {
+ label = "status:white:health_led";
+ gpios = <&gpio1 4 0>;
+ };
+ backup_led {
+ label = "status:blue:backup_led";
+ gpios = <&gpio0 15 0>;
+ };
+ };
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ Power {
+ label = "Power Button";
+ linux,code = <116>;
+ gpios = <&gpio0 14 1>;
+ };
+ Reset {
+ label = "Reset Button";
+ linux,code = <0x198>;
+ gpios = <&gpio0 12 1>;
+ };
+ OTB {
+ label = "OTB Button";
+ linux,code = <133>;
+ gpios = <&gpio1 3 1>;
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+ model = "Keymile Kirkwood Reference Design";
+ compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+
+ ocp@f1000000 {
+ serial@12000 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ nand@3000000 {
+ status = "ok";
+ chip-delay = <25>;
+ };
+ };
+};
Say 'Y' here if you want your kernel to support the
CompuLab CM-A510 Board.
+config MACH_DOVE_DT
+ bool "Marvell Dove Flattened Device Tree"
+ select USE_OF
+ help
+ Say 'Y' here if you want your kernel to support the
+ Marvell Dove using flattened device tree.
+
endmenu
endif
-obj-y += common.o addr-map.o irq.o pcie.o mpp.o
-
+obj-y += common.o addr-map.o irq.o mpp.o
+obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
+
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-dove-db.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cm-a510.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cubox.dtb
#include <linux/clk-provider.h>
#include <linux/ata_platform.h>
#include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/mach/time.h>
#include <asm/mach/pci.h>
#include <mach/dove.h>
+#include <mach/pm.h>
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
#include <plat/addr-map.h>
#include "common.h"
-static int get_tclk(void);
-
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
/*****************************************************************************
* CLK tree
****************************************************************************/
+static int dove_tclk;
+
+static DEFINE_SPINLOCK(gating_lock);
static struct clk *tclk;
-static void __init clk_init(void)
+static struct clk __init *dove_register_gate(const char *name,
+ const char *parent, u8 bit_idx)
{
- tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
- get_tclk());
+ return clk_register_gate(NULL, name, parent, 0,
+ (void __iomem *)CLOCK_GATING_CONTROL,
+ bit_idx, 0, &gating_lock);
+}
+
+static void __init dove_clk_init(void)
+{
+ struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+ struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+ struct clk *xor0, *xor1, *ge, *gephy;
- orion_clkdev_init(tclk);
+ tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
+ dove_tclk);
+
+ usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+ usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+ sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+ pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
+ pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+ sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+ sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+ nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+ camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+ i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+ i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+ crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+ ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+ pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+ xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+ xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+ gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+ ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+
+ orion_clkdev_add(NULL, "orion_spi.0", tclk);
+ orion_clkdev_add(NULL, "orion_spi.1", tclk);
+ orion_clkdev_add(NULL, "orion_wdt", tclk);
+ orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
+
+ orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+ orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+ orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
+ orion_clkdev_add("0", "sata_mv.0", sata);
+ orion_clkdev_add("0", "pcie", pex0);
+ orion_clkdev_add("1", "pcie", pex1);
+ orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+ orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+ orion_clkdev_add(NULL, "orion_nand", nand);
+ orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+ orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+ orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+ orion_clkdev_add(NULL, "mv_crypto", crypto);
+ orion_clkdev_add(NULL, "dove-ac97", ac97);
+ orion_clkdev_add(NULL, "dove-pdma", pdma);
+ orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
+ orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
}
/*****************************************************************************
orion_time_set_base(TIMER_VIRT_BASE);
}
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
{
- /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
return 166666667;
}
static void __init dove_timer_init(void)
{
+ dove_tclk = dove_find_tclk();
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
- IRQ_DOVE_BRIDGE, get_tclk());
+ IRQ_DOVE_BRIDGE, dove_tclk);
}
struct sys_timer dove_timer = {
.init = dove_timer_init,
};
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+ orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+ DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+
/*****************************************************************************
* XOR 0
****************************************************************************/
void __init dove_init(void)
{
- printk(KERN_INFO "Dove 88AP510 SoC, ");
- printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+ pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+ (dove_tclk + 499999) / 1000000);
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
dove_setup_cpu_mbus();
/* Setup root of clk tree */
- clk_init();
+ dove_clk_init();
/* internal devices that every board has */
dove_rtc_init();
while (1)
;
}
+
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+ OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+ OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+ OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+ NULL),
+ OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+ OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+ OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+ {},
+};
+
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+ .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static void __init dove_dt_init(void)
+{
+ pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+ (dove_tclk + 499999) / 1000000);
+
+#ifdef CONFIG_CACHE_TAUROS2
+ tauros2_init();
+#endif
+ dove_setup_cpu_mbus();
+
+ /* Setup root of clk tree */
+ dove_clk_init();
+
+ /* Internal devices not ported to DT yet */
+ dove_rtc_init();
+ dove_xor0_init();
+ dove_xor1_init();
+
+ dove_ge00_init(&dove_dt_ge00_data);
+ dove_ehci0_init();
+ dove_ehci1_init();
+ dove_pcie_init(1, 1);
+ dove_crypto_init();
+
+ of_platform_populate(NULL, of_default_bus_match_table,
+ dove_auxdata_lookup, NULL);
+}
+
+static const char * const dove_dt_board_compat[] = {
+ "marvell,dove",
+ NULL
+};
+
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+ .map_io = dove_map_io,
+ .init_early = dove_init_early,
+ .init_irq = orion_dt_init_irq,
+ .timer = &dove_timer,
+ .init_machine = dove_dt_init,
+ .restart = dove_restart,
+ .dt_compat = dove_dt_board_compat,
+MACHINE_END
+#endif
void dove_setup_cpu_mbus(void);
void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
void dove_sata_init(struct mv_sata_platform_data *sata_data);
+#ifdef CONFIG_PCI
void dove_pcie_init(int init_port0, int init_port1);
+#else
+static inline void dove_pcie_init(int init_port0, int init_port1) { }
+#endif
void dove_ehci0_init(void);
void dove_ehci1_init(void);
void dove_uart0_init(void);
#include <mach/irqs.h>
#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
-#define CLOCK_GATING_USB0_MASK (1 << 0)
-#define CLOCK_GATING_USB1_MASK (1 << 1)
-#define CLOCK_GATING_GBE_MASK (1 << 2)
-#define CLOCK_GATING_SATA_MASK (1 << 3)
-#define CLOCK_GATING_PCIE0_MASK (1 << 4)
-#define CLOCK_GATING_PCIE1_MASK (1 << 5)
-#define CLOCK_GATING_SDIO0_MASK (1 << 8)
-#define CLOCK_GATING_SDIO1_MASK (1 << 9)
-#define CLOCK_GATING_NAND_MASK (1 << 10)
-#define CLOCK_GATING_CAMERA_MASK (1 << 11)
-#define CLOCK_GATING_I2S0_MASK (1 << 12)
-#define CLOCK_GATING_I2S1_MASK (1 << 13)
-#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
-#define CLOCK_GATING_AC97_MASK (1 << 21)
-#define CLOCK_GATING_PDMA_MASK (1 << 22)
-#define CLOCK_GATING_XOR0_MASK (1 << 23)
-#define CLOCK_GATING_XOR1_MASK (1 << 24)
-#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
+#define CLOCK_GATING_BIT_USB0 0
+#define CLOCK_GATING_BIT_USB1 1
+#define CLOCK_GATING_BIT_GBE 2
+#define CLOCK_GATING_BIT_SATA 3
+#define CLOCK_GATING_BIT_PCIE0 4
+#define CLOCK_GATING_BIT_PCIE1 5
+#define CLOCK_GATING_BIT_SDIO0 8
+#define CLOCK_GATING_BIT_SDIO1 9
+#define CLOCK_GATING_BIT_NAND 10
+#define CLOCK_GATING_BIT_CAMERA 11
+#define CLOCK_GATING_BIT_I2S0 12
+#define CLOCK_GATING_BIT_I2S1 13
+#define CLOCK_GATING_BIT_CRYPTO 15
+#define CLOCK_GATING_BIT_AC97 21
+#define CLOCK_GATING_BIT_PDMA 22
+#define CLOCK_GATING_BIT_XOR0 23
+#define CLOCK_GATING_BIT_XOR1 24
+#define CLOCK_GATING_BIT_GIGA_PHY 30
+#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
+#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
+#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
+#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
+#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
+#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
+#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
+#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
+#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
+#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
+#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
+#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
+#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
+#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
+#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
+#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
+#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
+#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
or MV6282. If you have the wrong one, the buttons will not
work.
+config MACH_DOCKSTAR_DT
+ bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+ help
+ Say 'Y' here if you want your kernel to support the
+ Seagate FreeAgent Dockstar (Flattened Device Tree).
+
config MACH_GOFLEXNET_DT
bool "Seagate GoFlex Net (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
Flattened Device Tree.
+config MACH_IOMEGA_IX2_200_DT
+ bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+ help
+ Say 'Y' here if you want your kernel to support the
+ Iomega StorCenter ix2-200 (Flattened Device Tree).
+
+config MACH_KM_KIRKWOOD_DT
+ bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+ help
+ Say 'Y' here if you want your kernel to support the
+ Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+
config MACH_TS219
bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
help
obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o
obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o
obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o
obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
+obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
+
+dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
+dtb-$(CONFIG_MACH_DOCKSTAR_DT) += kirkwood-dockstar.dtb
+dtb-$(CONFIG_MACH_KM_KIRKWOOD_DT) += kirkwood-km_kirkwood.dtb
--- /dev/null
+/*
+ * arch/arm/mach-kirkwood/board-dockstar.c
+ *
+ * Seagate FreeAgent Dockstar Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+ .phy_addr = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+ MPP29_GPIO, /* USB Power Enable */
+ MPP46_GPIO, /* LED green */
+ MPP47_GPIO, /* LED orange */
+ 0
+};
+
+void __init dockstar_dt_init(void)
+{
+ /*
+ * Basic setup. Needs to be called early.
+ */
+ kirkwood_mpp_conf(dockstar_mpp_config);
+
+ if (gpio_request(29, "USB Power Enable") != 0 ||
+ gpio_direction_output(29, 1) != 0)
+ pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+ kirkwood_ehci_init();
+
+ kirkwood_ge00_init(&dockstar_ge00_data);
+}
if (of_machine_is_compatible("qnap,ts219"))
qnap_dt_ts219_init();
+ if (of_machine_is_compatible("seagate,dockstar"))
+ dockstar_dt_init();
+
if (of_machine_is_compatible("seagate,goflexnet"))
goflexnet_init();
if (of_machine_is_compatible("buffalo,lsxl"))
lsxl_init();
+ if (of_machine_is_compatible("iom,ix2-200"))
+ iomega_ix2_200_init();
+
+ if (of_machine_is_compatible("keymile,km_kirkwood"))
+ km_kirkwood_init();
+
of_platform_populate(NULL, kirkwood_dt_match_table,
kirkwood_auxdata_lookup, NULL);
}
"iom,iconnect",
"raidsonic,ib-nas62x0",
"qnap,ts219",
+ "seagate,dockstar",
"seagate,goflexnet",
"buffalo,lsxl",
+ "iom,ix2-200",
+ "keymile,km_kirkwood",
NULL
};
--- /dev/null
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+ .phy_addr = MV643XX_ETH_PHY_NONE,
+ .speed = SPEED_1000,
+ .duplex = DUPLEX_FULL,
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+ MPP12_GPIO, /* Reset Button */
+ MPP14_GPIO, /* Power Button */
+ MPP15_GPIO, /* Backup LED (blue) */
+ MPP16_GPIO, /* Power LED (white) */
+ MPP35_GPIO, /* OTB Button */
+ MPP36_GPIO, /* Rebuild LED (white) */
+ MPP37_GPIO, /* Health LED (red) */
+ MPP38_GPIO, /* SATA LED brightness control 1 */
+ MPP39_GPIO, /* SATA LED brightness control 2 */
+ MPP40_GPIO, /* Backup LED brightness control 1 */
+ MPP41_GPIO, /* Backup LED brightness control 2 */
+ MPP42_GPIO, /* Power LED brightness control 1 */
+ MPP43_GPIO, /* Power LED brightness control 2 */
+ MPP44_GPIO, /* Health LED brightness control 1 */
+ MPP45_GPIO, /* Health LED brightness control 2 */
+ MPP46_GPIO, /* Rebuild LED brightness control 1 */
+ MPP47_GPIO, /* Rebuild LED brightness control 2 */
+ 0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+ /*
+ * Basic setup. Needs to be called early.
+ */
+ kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+ kirkwood_ehci_init();
+
+ kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
+}
--- /dev/null
+/*
+ * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * arch/arm/mach-kirkwood/board-km_kirkwood.c
+ *
+ * Keymile km_kirkwood Reference Desing Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
+ .phy_addr = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int km_kirkwood_mpp_config[] __initdata = {
+ MPP8_GPIO, /* I2C SDA */
+ MPP9_GPIO, /* I2C SCL */
+ 0
+};
+
+void __init km_kirkwood_init(void)
+{
+ struct clk *sata_clk;
+ /*
+ * Basic setup. Needs to be called early.
+ */
+ kirkwood_mpp_conf(km_kirkwood_mpp_config);
+
+ /*
+ * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
+ * SATA bits (14-15) of the Clock Gating Control Register. Since these
+ * devices are also not present in this variant, their clocks get
+ * disabled because unused when clk_disable_unused() gets called.
+ * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
+ */
+ sata_clk = clk_get_sys("sata_mv.0", "0");
+ if (!IS_ERR(sata_clk))
+ sata_clk->flags |= CLK_IGNORE_UNUSED;
+ sata_clk = clk_get_sys("sata_mv.0", "1");
+ if (!IS_ERR(sata_clk))
+ sata_clk->flags |= CLK_IGNORE_UNUSED;
+
+ kirkwood_ehci_init();
+ kirkwood_ge00_init(&km_kirkwood_ge00_data);
+}
static inline void ib62x0_init(void) {};
#endif
+#ifdef CONFIG_MACH_DOCKSTAR_DT
+void dockstar_dt_init(void);
+#else
+static inline void dockstar_dt_init(void) {};
+#endif
+
#ifdef CONFIG_MACH_GOFLEXNET_DT
void goflexnet_init(void);
#else
static inline void lsxl_init(void) {};
#endif
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
+#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
+void km_kirkwood_init(void);
+#else
+static inline void km_kirkwood_init(void) {};
+#endif
+
/* early init functions not converted to fdt yet */
char *kirkwood_id(void);
void kirkwood_l2_init(void);
projects / firefly-linux-kernel-4.4.55.git / commitdiff