Add option to disable scheduling.

Destroy live-variable information after scheduling so it is
recomputed before later phases (e.g., reg. allocation).
Use deterministic iterator to enumerate sched graphs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1972 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index dafa8353bb3e837a2dee50bf4d5c19e14b9cfcd7..31eca3903b106c7375b2fbc66fb9f49f84e803bd 100644 (file)
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -31,6 +31,7 @@ using std::vector;
 cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
   "enable instruction scheduling debugging information",
   clEnumValN(Sched_NoDebugInfo,      "n", "disable debug output"),
+  clEnumValN(Sched_Disable,        "off", "disable instruction scheduling"),
   clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
   clEnumValN(Sched_PrintSchedTrace,  "t", "print trace of scheduling actions"),
   clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"), 0);
@@ -1491,58 +1492,71 @@ instrIsFeasible(const SchedulingManager& S,
 
 namespace {
   class InstructionSchedulingWithSSA : public MethodPass {
-    const TargetMachine &Target;
+    const TargetMachine &target;
   public:
-    inline InstructionSchedulingWithSSA(const TargetMachine &T) : Target(T) {}
-
+    inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
+  
     // getAnalysisUsageInfo - We use LiveVarInfo...
     virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
                                       Pass::AnalysisSet &Destroyed,
                                       Pass::AnalysisSet &Provided) {
       Requires.push_back(MethodLiveVarInfo::ID);
+      Destroyed.push_back(MethodLiveVarInfo::ID);
     }
+    
+    bool runOnMethod(Method *M);
+  };
+} // end anonymous namespace
+
 
-    bool runOnMethod(Method *M) {
-      cerr << "Instr scheduling failed for method " << ((Value*)M)->getName()
-           << "\n\n";
-      SchedGraphSet graphSet(M, Target);       
+bool
+InstructionSchedulingWithSSA::runOnMethod(Method *M)
+{
+  if (SchedDebugLevel == Sched_Disable)
+    return false;
   
-      if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
-        cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
-        graphSet.dump();
-      }
+  SchedGraphSet graphSet(M, target);   
   
-      for (SchedGraphSet::const_iterator GI=graphSet.begin();
-           GI != graphSet.end(); ++GI) {
-        SchedGraph* graph = GI->second;
-        const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
-        assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
-        const BasicBlock* bb = bbvec[0];
+  if (SchedDebugLevel >= Sched_PrintSchedGraphs)
+    {
+      cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
+      graphSet.dump();
+    }
+  
+  for (SchedGraphSet::const_iterator GI=graphSet.begin(), GE=graphSet.end();
+       GI != GE; ++GI)
+    {
+      SchedGraph* graph = (*GI);
+      const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
+      assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
+      const BasicBlock* bb = bbvec[0];
       
-        if (SchedDebugLevel >= Sched_PrintSchedTrace)
-          cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
+      if (SchedDebugLevel >= Sched_PrintSchedTrace)
+        cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
       
-        // expensive!
-        SchedPriorities schedPrio(M, graph, getAnalysis<MethodLiveVarInfo>());
-        SchedulingManager S(Target, graph, schedPrio);
-        
-        ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
-        
-        ForwardListSchedule(S);                             // computes schedule in S
-        
-        RecordSchedule(GI->first, S);                // records schedule in BB
-      }
-  
-      if (SchedDebugLevel >= Sched_PrintMachineCode) {
-        cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
-        MachineCodeForMethod::get(M).dump();
-      }
+      // expensive!
+      SchedPriorities schedPrio(M, graph,getAnalysis<MethodLiveVarInfo>());
+      SchedulingManager S(target, graph, schedPrio);
+          
+      ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
+      
+      ForwardListSchedule(S);               // computes schedule in S
+      
+      RecordSchedule(bb, S);                // records schedule in BB
+    }
   
-      return false;
+  if (SchedDebugLevel >= Sched_PrintMachineCode)
+    {
+      cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
+      MachineCodeForMethod::get(M).dump();
     }
-  };
-} // end anonymous namespace
+  
+  return false;
+}
+
 
-MethodPass *createInstructionSchedulingWithSSAPass(const TargetMachine &T) {
-  return new InstructionSchedulingWithSSA(T);
+MethodPass*
+createInstructionSchedulingWithSSAPass(const TargetMachine &tgt)
+{
+  return new InstructionSchedulingWithSSA(tgt);
 }

diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index dafa8353bb3e837a2dee50bf4d5c19e14b9cfcd7..31eca3903b106c7375b2fbc66fb9f49f84e803bd 100644 (file)
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -31,6 +31,7 @@ using std::vector;
 cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
   "enable instruction scheduling debugging information",
   clEnumValN(Sched_NoDebugInfo,      "n", "disable debug output"),
+  clEnumValN(Sched_Disable,        "off", "disable instruction scheduling"),
   clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
   clEnumValN(Sched_PrintSchedTrace,  "t", "print trace of scheduling actions"),
   clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"), 0);
@@ -1491,58 +1492,71 @@ instrIsFeasible(const SchedulingManager& S,
 
 namespace {
   class InstructionSchedulingWithSSA : public MethodPass {
-    const TargetMachine &Target;
+    const TargetMachine &target;
   public:
-    inline InstructionSchedulingWithSSA(const TargetMachine &T) : Target(T) {}
-
+    inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
+  
     // getAnalysisUsageInfo - We use LiveVarInfo...
     virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
                                       Pass::AnalysisSet &Destroyed,
                                       Pass::AnalysisSet &Provided) {
       Requires.push_back(MethodLiveVarInfo::ID);
+      Destroyed.push_back(MethodLiveVarInfo::ID);
     }
+    
+    bool runOnMethod(Method *M);
+  };
+} // end anonymous namespace
+
 
-    bool runOnMethod(Method *M) {
-      cerr << "Instr scheduling failed for method " << ((Value*)M)->getName()
-           << "\n\n";
-      SchedGraphSet graphSet(M, Target);       
+bool
+InstructionSchedulingWithSSA::runOnMethod(Method *M)
+{
+  if (SchedDebugLevel == Sched_Disable)
+    return false;
   
-      if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
-        cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
-        graphSet.dump();
-      }
+  SchedGraphSet graphSet(M, target);   
   
-      for (SchedGraphSet::const_iterator GI=graphSet.begin();
-           GI != graphSet.end(); ++GI) {
-        SchedGraph* graph = GI->second;
-        const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
-        assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
-        const BasicBlock* bb = bbvec[0];
+  if (SchedDebugLevel >= Sched_PrintSchedGraphs)
+    {
+      cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
+      graphSet.dump();
+    }
+  
+  for (SchedGraphSet::const_iterator GI=graphSet.begin(), GE=graphSet.end();
+       GI != GE; ++GI)
+    {
+      SchedGraph* graph = (*GI);
+      const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
+      assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
+      const BasicBlock* bb = bbvec[0];
       
-        if (SchedDebugLevel >= Sched_PrintSchedTrace)
-          cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
+      if (SchedDebugLevel >= Sched_PrintSchedTrace)
+        cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
       
-        // expensive!
-        SchedPriorities schedPrio(M, graph, getAnalysis<MethodLiveVarInfo>());
-        SchedulingManager S(Target, graph, schedPrio);
-        
-        ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
-        
-        ForwardListSchedule(S);                             // computes schedule in S
-        
-        RecordSchedule(GI->first, S);                // records schedule in BB
-      }
-  
-      if (SchedDebugLevel >= Sched_PrintMachineCode) {
-        cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
-        MachineCodeForMethod::get(M).dump();
-      }
+      // expensive!
+      SchedPriorities schedPrio(M, graph,getAnalysis<MethodLiveVarInfo>());
+      SchedulingManager S(target, graph, schedPrio);
+          
+      ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
+      
+      ForwardListSchedule(S);               // computes schedule in S
+      
+      RecordSchedule(bb, S);                // records schedule in BB
+    }
   
-      return false;
+  if (SchedDebugLevel >= Sched_PrintMachineCode)
+    {
+      cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
+      MachineCodeForMethod::get(M).dump();
     }
-  };
-} // end anonymous namespace
+  
+  return false;
+}
+
 
-MethodPass *createInstructionSchedulingWithSSAPass(const TargetMachine &T) {
-  return new InstructionSchedulingWithSSA(T);
+MethodPass*
+createInstructionSchedulingWithSSAPass(const TargetMachine &tgt)
+{
+  return new InstructionSchedulingWithSSA(tgt);
 }