const TargetRegisterClass *RC = NULL;
switch (VT.getSimpleVT().SimpleTy) {
default: return false;
+ case MVT::i1:
case MVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
switch (VT.getSimpleVT().SimpleTy) {
case MVT::f80: // No f80 support yet.
default: return false;
+ case MVT::i1: {
+ // Mask out all but lowest bit.
+ unsigned AndResult = createResultReg(X86::GR8RegisterClass);
+ BuildMI(MBB, DL,
+ TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
+ Val = AndResult;
+ }
+ // FALLTHROUGH, handling i1 as i8.
case MVT::i8: Opc = X86::MOV8mr; break;
case MVT::i16: Opc = X86::MOV16mr; break;
case MVT::i32: Opc = X86::MOV32mr; break;
// If this is a store of a simple constant, fold the constant into the store.
if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
unsigned Opc = 0;
+ bool Signed = true;
switch (VT.getSimpleVT().SimpleTy) {
default: break;
+ case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
case MVT::i8: Opc = X86::MOV8mi; break;
case MVT::i16: Opc = X86::MOV16mi; break;
case MVT::i32: Opc = X86::MOV32mi; break;
if (Opc) {
addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
- .addImm(CI->getSExtValue());
+ .addImm(Signed ? CI->getSExtValue() :
+ CI->getZExtValue());
return true;
}
}
/// X86SelectStore - Select and emit code to implement store instructions.
bool X86FastISel::X86SelectStore(Instruction* I) {
EVT VT;
- if (!isTypeLegal(I->getOperand(0)->getType(), VT))
+ if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
return false;
X86AddressMode AM;
///
bool X86FastISel::X86SelectLoad(Instruction *I) {
EVT VT;
- if (!isTypeLegal(I->getType(), VT))
+ if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
return false;
X86AddressMode AM;