Reorder some members in MCRegisterClass to remove padding on 64-bit builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/MC/MCRegisterInfo.h b/include/llvm/MC/MCRegisterInfo.h
index c4c6ccf9b23ae77403844685287d804d7330fbc0..0ffc73c79ee43b021f6154eb202830c4d7e51501 100644 (file)
--- a/include/llvm/MC/MCRegisterInfo.h
+++ b/include/llvm/MC/MCRegisterInfo.h
@@ -28,14 +28,14 @@ public:
   typedef const unsigned* iterator;
   typedef const unsigned* const_iterator;
 
-  unsigned ID;
+  const unsigned ID;
   const char *Name;
   const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
   const int CopyCost;
   const bool Allocatable;
   const iterator RegsBegin;
-  unsigned RegsSize;
   const unsigned char *const RegSet;
+  const unsigned RegsSize;
   const unsigned RegSetSize;
 
   /// getID() - Return the register class ID number.

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 7e41a110e73f566e7f6dfa8c31a798ff1e3442a1..1193f1cc316e95a07001feb213a1c36cfb3adbcc 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -391,8 +391,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
        << RC.SpillAlignment/8 << ", "
        << RC.CopyCost << ", "
        << RC.Allocatable << ", "
-       << RC.getName() << ", " << RC.getOrder().size() << ", "
-       << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits) },\n";
+       << RC.getName() << ", " << RC.getName() << "Bits, "
+       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits) },\n";
   }
 
   OS << "};\n\n";