Reverted r99376. The disassembler will deal with the 2-reg format of these two

N3VX instructions using special case code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99409 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index dd0e3daac73f2e550c26eb8328960efa29482f35..7f0fdad5ab3d416a408be85c7adf9903dfdf73d6 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -2778,13 +2778,10 @@ def  VSWPq    : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
 
 //   VMOV     : Vector Move (Register)
 
-// Mark these as 2-register instructions to help the disassembler.
-let F = N2RegFrm, Form = N2RegFrm.Value in {
 def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
                      IIC_VMOVD, "vmov", "$dst, $src", "", []>;
 def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
                      IIC_VMOVD, "vmov", "$dst, $src", "", []>;
-}
 
 //   VMOV     : Vector Move (Immediate)