add some comments that describe what we model

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26588 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index cd02705feeaf65a74a320d822c32763fd8d8fd62..1b1559546b2c5db77b3afbb153851176eef70564 100644 (file)
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -22,6 +22,24 @@ using namespace llvm;
 //===----------------------------------------------------------------------===//
 // PowerPC 970 Hazard Recognizer
 //
+// This models the dispatch group formation of the PPC970 processor.  Dispatch
+// groups are bundles of up to five instructions that can contain up to two ALU
+// (aka FXU) ops, two FPU ops, two Load/Store ops, one CR op, one VALU op, one
+// VPERM op, and one BRANCH op.  If the code contains more instructions in a
+// sequence than the dispatch group can contain (e.g. three loads in a row) the
+// processor terminates the dispatch group early, wasting execution resources.
+//
+// In addition to these restrictions, there are a number of other restrictions:
+// some instructions, e.g. branches, are required to be the last instruction in
+// a group.  Additionally, only branches can issue in the 5th (last) slot.
+//
+// Finally, there are a number of "structural" hazards on the PPC970.  These
+// conditions cause large performance penalties due to misprediction, recovery,
+// and replay logic that has to happen.  These cases include setting a CTR and
+// branching through it in the same dispatch group, and storing to an address,
+// then loading from the same address within a dispatch group.  To avoid these
+// conditions, we insert no-op instructions when appropriate.
+//
 // FIXME: This is missing some significant cases:
 //   0. Handling of instructions that must be the first/last in a group.
 //   1. Modeling of microcoded instructions.
@@ -30,9 +48,6 @@ using namespace llvm;
 //   4. Handling of the esoteric cases in "Resource-based Instruction Grouping",
 //      e.g. integer divides that only execute in the second slot.
 //
-// Note: on the PPC970, logical CR operations are more expensive in their three
-// address form: ops that read/write the same register are half as expensive as
-//
 
 void PPCHazardRecognizer970::EndDispatchGroup() {
   DEBUG(std::cerr << "=== Start of dispatch group\n");