let Inst{19-16} = addr{16-13}; // Rn
let Inst{11-0} = addr{11-0}; // imm12
let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
+ let DecoderMethod = "DecodeSTRPreImm";
}
def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
let Inst{11-0} = addr{11-0};
let Inst{4} = 0; // Inst{4} = 0
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+ let DecoderMethod = "DecodeSTRPreReg";
}
def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
uint64_t Address, const void *Decoder);
static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder);
return true;
}
+static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned imm = fieldFromInstruction32(Insn, 0, 12);
+ imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
+ imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
+ unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+ if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
+
+ if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+ if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false;
+ if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+
+ return true;
+}
+
+static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned imm = fieldFromInstruction32(Insn, 0, 12);
+ imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
+ imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
+ unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+
+ if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
+
+ if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+ if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false;
+ if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+
+ return true;
+}