drm/radeon/dce6: add missing display reg for tiling setup

A new tiling config register for the display blocks was
added on DCE6.

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=62889
https://bugs.freedesktop.org/show_bug.cgi?id=57919

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 27769e724b6de1d238fc402b844d056ed69bb4b8..02e9580636829f2b09eefca2c426e68c6a8d61b6 100644 (file)
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -621,6 +621,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
        WREG32(GB_ADDR_CONFIG, gb_addr_config);
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+       if (ASIC_IS_DCE6(rdev))
+               WREG32(DMIF_ADDR_CALC, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 079dee202a9e4f371653de255259023c5cf1ad9b..445b235c4323e321787d4b9369aee2376e9a4a94 100644 (file)
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -45,6 +45,10 @@
 #define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
 
 #define DMIF_ADDR_CONFIG                               0xBD4
+
+/* DCE6 only */
+#define DMIF_ADDR_CALC                                 0xC00
+
 #define        SRBM_GFX_CNTL                                   0x0E44
 #define                RINGID(x)                                       (((x) & 0x3) << 0)
 #define                VMID(x)                                         (((x) & 0x7) << 0)

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 862b52c69882980e1b62bde55224a90fe13aa889..ace45da914347d569b7026ccb9917c625a15d5ba 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1765,6 +1765,7 @@ static void si_gpu_init(struct radeon_device *rdev)
 
        WREG32(GB_ADDR_CONFIG, gb_addr_config);
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+       WREG32(DMIF_ADDR_CALC, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 23fc08fc8e7fb70d65068e01cabfa42d2df755b2..f84cff0aafcc3bd2297d7af956acc2d509d47133 100644 (file)
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -65,6 +65,8 @@
 
 #define DMIF_ADDR_CONFIG                               0xBD4
 
+#define DMIF_ADDR_CALC                                 0xC00
+
 #define        SRBM_STATUS                                     0xE50
 #define                GRBM_RQ_PENDING                         (1 << 5)
 #define                VMC_BUSY                                (1 << 8)