fix an f32/f64 type mismatch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23587 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index fdefef7c23730bf23bd3ce91428d685ae05d3ec0..9bab6ed8be336464b6ff1c16678a3a8b16861f06 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -130,13 +130,17 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   default: assert(0 && "Wasn't expecting to be able to lower this!"); 
   case ISD::FP_TO_SINT: {
     assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
+    SDOperand Src = Op.getOperand(0);
+    if (Src.getValueType() == MVT::f32)
+      Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
+    
     switch (Op.getValueType()) {
     default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
     case MVT::i32:
-      Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0));
+      Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
       break;
     case MVT::i64:
-      Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0));
+      Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
       break;
     }