STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the...

Found by randomized testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 40a7936cfe28132936b7e0b7433a6127bd1bb528..a57102c6e1464bcd74024977c6f5376cc10863c9 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -927,6 +927,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::STC2L_OPTION:
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       break;
     default:
       Inst.addOperand(MCOperand::CreateReg(0));
@@ -946,6 +948,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
   switch (Inst.getOpcode()) {
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       imm |= U << 8;
     case ARM::LDC_OPTION:
     case ARM::LDCL_OPTION:

diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index cf258759379ad6d0f2562183ecfa702386d16143..66bec91c31fec2c858359c05a88752a387e9f41b 100644 (file)
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -314,3 +314,6 @@
 
 # CHECK: rfedb #4!
 0x14 0x0 0x32 0xf9
+
+# CHECK: stc2l p0, cr0, [r2], #-96
+0x18 0x0 0x62 0xfc