Use ZERO_EXTEND instead of ANY_EXTEND when promoting

shift amounts, to avoid implicitly assuming that
target architectures will ignore the high bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63169 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 58ac8c285c954c7ee9cac34e32c43fbd22b98a83..4ee17bf807c02c20553cb73a78cdb39a8df29267 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -974,7 +974,7 @@ SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) {
     return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
 
   if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
-    return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
+    return DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
 
   return ShiftAmt;
 }

diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 3823f65263a12f6473532aec008d3793bb997f70..420a8d374c683bb9dddcbbfc33723ed8b1445df8 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -114,7 +114,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) {
   if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
     ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
   else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
-    ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
+    ShiftAmt = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
 
   return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt);
 }