MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26234 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 85aa669ae0c789514a9578d9a5a6151932ca7bc6..e061c81a9c1c56254c142c3bf58b61daf88b7b55 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -3013,10 +3013,10 @@ def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
 // XMM Packed Floating point support (requires SSE / SSE2)
 //===----------------------------------------------------------------------===//
 
-def MOVAPSrr : I<0x28, MRMSrcMem, (ops V4F4:$dst, V4F4:$src),
+def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
                 "movaps {$src, $dst|$dst, $src}", []>,
                Requires<[HasSSE1]>, TB;
-def MOVAPDrr : I<0x28, MRMSrcMem, (ops V2F8:$dst, V2F8:$src),
+def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
                 "movapd {$src, $dst|$dst, $src}", []>,
                Requires<[HasSSE2]>, TB, OpSize;