Teach DAGISelEmitter about zero_reg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37900 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index 17114b0ebaee0d6c114d71faf501200e571e6a64..ca3d37a85a10a6b25a0936980a3a95ad45a0968d 100644 (file)
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -622,7 +622,8 @@ static std::vector<unsigned char> getImplicitType(Record *R, bool NotRegisters,
   } else if (R->getName() == "ptr_rc") {
     Other[0] = MVT::iPTR;
     return Other;
-  } else if (R->getName() == "node" || R->getName() == "srcvalue") {
+  } else if (R->getName() == "node" || R->getName() == "srcvalue" ||
+             R->getName() == "zero_reg") {
     // Placeholder.
     return Unknown;
   }
@@ -2711,6 +2712,12 @@ public:
                    getEnumName(N->getTypeNum(0)) + ");");
           NodeOps.push_back("Tmp" + utostr(ResNo));
           return NodeOps;
+        } else if (DI->getDef()->getName() == "zero_reg") {
+          emitCode("SDOperand Tmp" + utostr(ResNo) +
+                   " = CurDAG->getRegister(0, " +
+                   getEnumName(N->getTypeNum(0)) + ");");
+          NodeOps.push_back("Tmp" + utostr(ResNo));
+          return NodeOps;
         }
       } else if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
         unsigned ResNo = TmpNo++;