rk32 edp:remove unused code
authoryxj <yxj@rock-chips.com>
Fri, 7 Mar 2014 02:57:39 +0000 (10:57 +0800)
committeryxj <yxj@rock-chips.com>
Thu, 13 Mar 2014 03:27:51 +0000 (11:27 +0800)
drivers/video/rockchip/transmitter/rk32_dp.c
drivers/video/rockchip/transmitter/rk32_dp.h
drivers/video/rockchip/transmitter/rk32_dp_reg.c

index d3bf948b490d85baf7efdf4c816a2707d317cc60..c6c08ed9e275665e8608ab121e369ecdb21c47be 100644 (file)
 
 static int rk32_edp_init_edp(struct rk32_edp *edp)
 {
+       struct rk_screen *screen = &edp->screen;
+       u32 val = 0;
+#ifndef CONFIG_RK_FPGA
+       if (screen->lcdc_id == 0)  /*select lcdc*/
+               val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
+       else
+               val = EDP_SEL_VOP_LIT << 16;
+       writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
+#endif
        rk32_edp_reset(edp);
-       rk32_edp_init_analog_param(edp);
+       rk32_edp_init_refclk(edp);
        rk32_edp_init_interrupt(edp);
 
        rk32_edp_enable_sw_function(edp);
@@ -1075,8 +1084,6 @@ edp_phy_init:
                goto out;
        }
 
-       rk32_edp_disable_rx_zmux(edp);
-
        
        ret = rk32_edp_enable_scramble(edp, 0);
        if (ret) {
@@ -1091,9 +1098,6 @@ edp_phy_init:
        }
        rk32_edp_enable_enhanced_mode(edp, 0);
 
-       
-       rk32_edp_rx_control(edp,0);
-
        /* Link Training */
        ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
        if (ret) {
@@ -1101,9 +1105,6 @@ edp_phy_init:
                goto out;
        }
 
-       /* Rx data enable */
-       rk32_edp_rx_control(edp,1);
-
        rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
        rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
 
@@ -1188,12 +1189,20 @@ static int rk32_edp_probe(struct platform_device *pdev)
        }
        platform_set_drvdata(pdev, edp);
        dev_set_name(edp->dev, "rk32-edp");
+       
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        edp->regs = devm_ioremap_resource(&pdev->dev, res);
        if (IS_ERR(edp->regs)) {
                dev_err(&pdev->dev, "ioremap reg failed\n");
                return PTR_ERR(edp->regs);
        }
+
+       
+       edp->irq = platform_get_irq(pdev, 0);
+       if (edp->irq < 0) {
+               dev_err(&pdev->dev, "cannot find IRQ\n");
+               return edp->irq;
+       }
        ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
                        dev_name(&pdev->dev), edp);
        if (ret) {
index de5632ff6d259b52d020b0b2b965ba79fafe8630..f84757cfc71d09ad073ac392550d7f986ce145b6 100644 (file)
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+
+
 #define REF_CLK_FROM_INTER                     (1 << 4)
+#define GRF_EDP_HDCP_EN                                (1 << 15)
+#define GRF_EDP_BIST_EN                                (1 << 14)
+#define GRF_EDP_MEM_CTL_BY_EDP                 (1 << 13)
+#define GRF_EDP_SECURE_EN                      (1 << 3)
+#define EDP_SEL_VOP_LIT                                (1 << 5)
 enum color_coefficient {
        COLOR_YCBCR601,
        COLOR_YCBCR709
@@ -487,8 +494,9 @@ struct rk32_edp {
        struct device           *dev;
        void __iomem            *regs;
        unsigned int            irq;
-       struct clk              *clk_edp;
-       struct clk              *clk_24m;
+       struct clk              *clk_edp;  /*clk for edp controller*/
+       struct clk              *clk_24m;  /*clk for edp phy*/
+       struct clk              *pclk;     /*clk for phb bus*/
        struct link_train       link_train;
        struct video_info       video_info;
        struct rk_screen        screen;
@@ -499,7 +507,7 @@ struct rk32_edp {
 void rk32_edp_enable_video_mute(struct rk32_edp *edp, bool enable);
 void rk32_edp_stop_video(struct rk32_edp *edp);
 void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable);
-void rk32_edp_init_analog_param(struct rk32_edp *edp);
+void rk32_edp_init_refclk(struct rk32_edp *edp);
 void rk32_edp_init_interrupt(struct rk32_edp *edp);
 void rk32_edp_reset(struct rk32_edp *edp);
 void rk32_edp_config_interrupt(struct rk32_edp *edp);
index 00fb1cec57000f52faf30e4bd40b816a8bbfeadd..d8f979b4ea5e0ec9fc9d04db0ea9a1b85f1626ea 100644 (file)
@@ -59,7 +59,7 @@ void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable)
        writel(val, edp->regs + LANE_MAP);
 }
 
-void rk32_edp_init_analog_param(struct rk32_edp *edp)
+void rk32_edp_init_refclk(struct rk32_edp *edp)
 {
        u32 val;
        /*struct rk32_edp_platdata *pdata = edp->dev->platform_data;
@@ -1152,11 +1152,15 @@ int rk32_edp_bist_cfg(struct rk32_edp *edp)
        val = BIST_EN;
        writel(val, edp->regs + VIDEO_CTL_4);
 
+#ifndef CONFIG_RK_FPGA
+       val = (GRF_EDP_BIST_EN << 16) | GRF_EDP_BIST_EN;
+       writel_relaxed(val,RK_GRF_VIRT + RK3288_GRF_SOC_CON8);
+#endif
+
+
        val = readl(edp->regs + VIDEO_CTL_10);
        val &= ~F_SEL;
        writel(val, edp->regs + VIDEO_CTL_10);
-
-       rk32_edp_start_video(edp);
        
        return 0;