Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool

would have been a Godsend here!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index e0fa519d62b31ab0008f44d3466f5c9b7989623e..dbf77475aad64fc630d9d8178d3277a951690130 100644 (file)
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -48,7 +48,7 @@ class Type;
 /// register, e.g. RAX, EAX, are super-registers of AX.
 ///
 struct TargetRegisterDesc {
-  const char     *Name;         // Assembly language name for the register
+  const char     *AsmName;      // Assembly language name for the register
   const char     *PrintableName;// Printable name for the reg (for debugging)
   const unsigned *AliasSet;     // Register Alias Set, described above
   const unsigned *SubRegs;      // Sub-register set, described above
@@ -376,10 +376,10 @@ public:
     return get(RegNo).SuperRegs;
   }
 
-  /// getName - Return the symbolic target specific name for the specified
-  /// physical register.
-  const char *getName(unsigned RegNo) const {
-    return get(RegNo).Name;
+  /// getAsmName - Return the symbolic target specific name for the
+  /// specified physical register.
+  const char *getAsmName(unsigned RegNo) const {
+    return get(RegNo).AsmName;
   }
 
   /// getPrintableName - Return the human-readable symbolic target specific name

diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp
index 48c25a14a3506a687fd0bc88b31758599c1bb50b..cc932451ace83e590aa0666dd812ca1cd2516a22 100644 (file)
--- a/lib/CodeGen/LiveInterval.cpp
+++ b/lib/CodeGen/LiveInterval.cpp
@@ -665,7 +665,7 @@ void LiveRange::dump() const {
 void LiveInterval::print(std::ostream &OS,
                          const TargetRegisterInfo *TRI) const {
   if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
-    OS << TRI->getName(reg);
+    OS << TRI->getPrintableName(reg);
   else
     OS << "%reg" << reg;
 

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 716c3701102f1b45c358e4328b2c31baa1570786..8ffffe1601877224e61f64c6a2787a50e9d3a1b3 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -189,7 +189,7 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li,
 
 void LiveIntervals::printRegName(unsigned reg) const {
   if (TargetRegisterInfo::isPhysicalRegister(reg))
-    cerr << tri_->getName(reg);
+    cerr << tri_->getPrintableName(reg);
   else
     cerr << "%reg" << reg;
 }

diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index dc6a618d34c782fffa5e7d1781a908ab7e60ea5d..5ca18d086acc2aa16f4a27c0fb1486d97e598a56 100644 (file)
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -146,7 +146,7 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
                              const TargetRegisterInfo *TRI = 0) {
   if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
     if (TRI)
-      os << " %" << TRI->get(RegNo).Name;
+      os << " %" << TRI->get(RegNo).PrintableName;
     else
       os << " %mreg(" << RegNo << ")";
   } else

diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index 30896172883e431b5d45ed6305b243900a359d00..1e0171a39f650b9171feda3c5c4285e1bc7e9391 100644 (file)
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -214,7 +214,7 @@ void MachineFunction::print(std::ostream &OS) const {
     for (MachineRegisterInfo::livein_iterator
          I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
       if (TRI)
-        OS << " " << TRI->getName(I->first);
+        OS << " " << TRI->getPrintableName(I->first);
       else
         OS << " Reg #" << I->first;
       
@@ -228,7 +228,7 @@ void MachineFunction::print(std::ostream &OS) const {
     for (MachineRegisterInfo::liveout_iterator
          I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
       if (TRI)
-        OS << " " << TRI->getName(*I);
+        OS << " " << TRI->getPrintableName(*I);
       else
         OS << " Reg #" << *I;
     OS << "\n";

diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index 89ab93df0a63b133b905419145069041e38ee850..dcca8856d284eef375ba488663ae07a0bdc6c3c9 100644 (file)
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -251,7 +251,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
         const TargetRegisterInfo *TRI = TM->getRegisterInfo();
         for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
              *ImpUses; ++ImpUses)
-          DOUT << "      -> " << TRI->getName(*ImpUses) << "\n";
+          DOUT << "      -> " << TRI->getPrintableName(*ImpUses) << "\n";
       }
 
       if (I.getDesc().getImplicitDefs()) {
@@ -260,7 +260,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
         const TargetRegisterInfo *TRI = TM->getRegisterInfo();
         for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
              *ImpDefs; ++ImpDefs)
-          DOUT << "      -> " << TRI->getName(*ImpDefs) << "\n";
+          DOUT << "      -> " << TRI->getPrintableName(*ImpDefs) << "\n";
       }
 
         //if (TII->hasUnmodelledSideEffects(&I))

diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index 0c6c25439a7794c461884db329e8ac6fceac6219..efd86bf8194cb29d280bfd89dd61a7f7577df70e 100644 (file)
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -311,7 +311,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
   assert(VirtReg && "Spilling a physical register is illegal!"
          " Must not have appropriate kill for the register or use exists beyond"
          " the intended one.");
-  DOUT << "  Spilling register " << RegInfo->getName(PhysReg)
+  DOUT << "  Spilling register " << RegInfo->getPrintableName(PhysReg)
        << " containing %reg" << VirtReg;
   
   const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@@ -535,7 +535,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
   markVirtRegModified(VirtReg, false);
 
   DOUT << "  Reloading %reg" << VirtReg << " into "
-       << RegInfo->getName(PhysReg) << "\n";
+       << RegInfo->getPrintableName(PhysReg) << "\n";
 
   // Add move instruction(s)
   TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
@@ -646,7 +646,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
           DOUT << "  Regs have values: ";
           for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
             if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
-               DOUT << "[" << RegInfo->getName(i)
+               DOUT << "[" << RegInfo->getPrintableName(i)
                     << ",%reg" << PhysRegsUsed[i] << "] ";
           DOUT << "\n");
 
@@ -700,14 +700,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT << "  Last use of " << RegInfo->getName(PhysReg)
+        DOUT << "  Last use of " << RegInfo->getPrintableName(PhysReg)
              << "[%reg" << VirtReg <<"], removing it from live set\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
             DOUT  << "  Last use of "
-                  << RegInfo->getName(*AliasSet)
+                  << RegInfo->getPrintableName(*AliasSet)
                   << "[%reg" << VirtReg <<"], removing it from live set\n";
             removePhysReg(*AliasSet);
           }
@@ -806,14 +806,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT  << "  Register " << RegInfo->getName(PhysReg)
+        DOUT  << "  Register " << RegInfo->getPrintableName(PhysReg)
               << " [%reg" << VirtReg
               << "] is never used, removing it frame live list\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
-            DOUT  << "  Register " << RegInfo->getName(*AliasSet)
+            DOUT  << "  Register " << RegInfo->getPrintableName(*AliasSet)
                   << " [%reg" << *AliasSet
                   << "] is never used, removing it frame live list\n";
             removePhysReg(*AliasSet);

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index f4f994c9e73d1bc74d4cda881b16ea951bc74162..aa042c75c1fcf624ac8cfdacfd7b49de83f343e4 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -164,7 +164,7 @@ namespace {
         if (TargetRegisterInfo::isVirtualRegister(reg)) {
           reg = vrm_->getPhys(reg);
         }
-        DOUT << tri_->getName(reg) << '\n';
+        DOUT << tri_->getPrintableName(reg) << '\n';
       }
     }
   };
@@ -239,7 +239,8 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
 
   // Try to coalesce.
   if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
-    DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n';
+    DOUT << "Coalescing: " << cur << " -> " << tri_->getPrintableName(SrcReg)
+         << '\n';
     vrm_->clearVirt(cur.reg);
     vrm_->assignVirt2Phys(cur.reg, SrcReg);
     ++NumCoalesce;
@@ -627,7 +628,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   // the free physical register and add this interval to the active
   // list.
   if (physReg) {
-    DOUT <<  tri_->getName(physReg) << '\n';
+    DOUT <<  tri_->getPrintableName(physReg) << '\n';
     vrm_->assignVirt2Phys(cur->reg, physReg);
     prt_->addRegUse(physReg);
     active_.push_back(std::make_pair(cur, cur->begin()));
@@ -689,7 +690,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   }
   
   DOUT << "\t\tregister with min weight: "
-       << tri_->getName(minReg) << " (" << minWeight << ")\n";
+       << tri_->getPrintableName(minReg) << " (" << minWeight << ")\n";
 
   // if the current has the minimum weight, we need to spill it and
   // add any added intervals back to unhandled, and restart
@@ -868,11 +869,11 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   if (cur->preference) {
     if (prt_->isRegAvail(cur->preference)) {
       DOUT << "\t\tassigned the preferred register: "
-           << tri_->getName(cur->preference) << "\n";
+           << tri_->getPrintableName(cur->preference) << "\n";
       return cur->preference;
     } else
       DOUT << "\t\tunable to assign the preferred register: "
-           << tri_->getName(cur->preference) << "\n";
+           << tri_->getPrintableName(cur->preference) << "\n";
   }
 
   // Scan for the first available register.

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 99fc6c9028ab7ba4a6d9b3e55c8af02570ba3e2e..bcadf89fe5c9792bd54e4ee173fd25eb5bcb14da 100644 (file)
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -286,7 +286,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
   assert(VirtReg && "Spilling a physical register is illegal!"
          " Must not have appropriate kill for the register or use exists beyond"
          " the intended one.");
-  DOUT << "  Spilling register " << TRI->getName(PhysReg)
+  DOUT << "  Spilling register " << TRI->getPrintableName(PhysReg)
        << " containing %reg" << VirtReg;
   
   const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@@ -502,7 +502,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
   markVirtRegModified(VirtReg, false);   // Note that this reg was just reloaded
 
   DOUT << "  Reloading %reg" << VirtReg << " into "
-       << TRI->getName(PhysReg) << "\n";
+       << TRI->getPrintableName(PhysReg) << "\n";
 
   // Add move instruction(s)
   const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@@ -575,7 +575,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
           DOUT << "  Regs have values: ";
           for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
             if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
-               DOUT << "[" << TRI->getName(i)
+               DOUT << "[" << TRI->getPrintableName(i)
                     << ",%reg" << PhysRegsUsed[i] << "] ";
           DOUT << "\n");
 
@@ -637,14 +637,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT << "  Last use of " << TRI->getName(PhysReg)
+        DOUT << "  Last use of " << TRI->getPrintableName(PhysReg)
              << "[%reg" << VirtReg <<"], removing it from live set\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
             DOUT  << "  Last use of "
-                  << TRI->getName(*AliasSet)
+                  << TRI->getPrintableName(*AliasSet)
                   << "[%reg" << VirtReg <<"], removing it from live set\n";
             removePhysReg(*AliasSet);
           }
@@ -728,7 +728,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
         MF->getRegInfo().setPhysRegUsed(DestPhysReg);
         markVirtRegModified(DestVirtReg);
         getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
-        DOUT << "  Assigning " << TRI->getName(DestPhysReg)
+        DOUT << "  Assigning " << TRI->getPrintableName(DestPhysReg)
              << " to %reg" << DestVirtReg << "\n";
         MI->getOperand(i).setReg(DestPhysReg);  // Assign the output register
       }
@@ -751,14 +751,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
       }
 
       if (PhysReg) {
-        DOUT  << "  Register " << TRI->getName(PhysReg)
+        DOUT  << "  Register " << TRI->getPrintableName(PhysReg)
               << " [%reg" << VirtReg
               << "] is never used, removing it frame live list\n";
         removePhysReg(PhysReg);
         for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
-            DOUT  << "  Register " << TRI->getName(*AliasSet)
+            DOUT  << "  Register " << TRI->getPrintableName(*AliasSet)
                   << " [%reg" << *AliasSet
                   << "] is never used, removing it frame live list\n";
             removePhysReg(*AliasSet);

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 8da6f79f5bf5a891755560dfd2df0a11734243ba..cbc54cc54b101cc32ff01342b63d68c2f39c216f 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4181,7 +4181,8 @@ void SDNode::dump(const SelectionDAG *G) const {
   } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
     if (G && R->getReg() &&
         TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
-      cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg());
+      cerr << " "
+           << G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
     } else {
       cerr << " #" << R->getReg();
     }

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 2d6d0405573ef9832694b37565fd269cf939cee3..73871863339a96c3b9b52cd243807ffab7f61fb5 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -133,7 +133,8 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
   } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) {
     if (G && R->getReg() != 0 &&
         TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
-      Op = Op + " " + G->getTarget().getRegisterInfo()->getName(R->getReg());
+      Op = Op + " " +
+       G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
     } else {
       Op += " #" + utostr(R->getReg());
     }

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 22e2117bad8435617ef4a3aa820bed42524c5200..43e8969c0879ad653ae9e1c7e681abfb80dc7279 100644 (file)
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1648,7 +1648,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
     
     for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 
          I != E; ++I) {
-      if (StringsEqualNoCase(RegName, RI->get(*I).Name))
+      if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
         return std::make_pair(*I, RC);
     }
   }

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index f015ad5c1f391d35820b1bbde76e3fcba358673d..3d777e39c4bb4760910f5582fa46729dce8ad359 100644 (file)
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1537,7 +1537,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
 
 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
   if (TargetRegisterInfo::isPhysicalRegister(reg))
-    cerr << tri_->getName(reg);
+    cerr << tri_->getPrintableName(reg);
   else
     cerr << "%reg" << reg;
 }

diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 48e5a16a509ae17e69844a04d9112699c5737355..93a584b7a9b0ddd64c2528238d9419fd380ede81 100644 (file)
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -141,8 +141,8 @@ void VirtRegMap::print(std::ostream &OS) const {
   for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
          e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
     if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
-      OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n";
-
+      OS << "[reg" << i << " -> " << TRI->getPrintableName(Virt2PhysMap[i])
+         << "]\n";
   }
 
   for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
@@ -351,7 +351,7 @@ public:
       DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
     else
       DOUT << "Remembering SS#" << SlotOrReMat;
-    DOUT << " in physreg " << TRI->getName(Reg) << "\n";
+    DOUT << " in physreg " << TRI->getPrintableName(Reg) << "\n";
   }
 
   /// canClobberPhysReg - Return true if the spiller is allowed to change the 
@@ -392,7 +392,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
     assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
            "Bidirectional map mismatch!");
     SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
-    DOUT << "PhysReg " << TRI->getName(PhysReg)
+    DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
          << " copied, it is available for use but can no longer be modified\n";
   }
 }
@@ -417,7 +417,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
     assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
            "Bidirectional map mismatch!");
     SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
-    DOUT << "PhysReg " << TRI->getName(PhysReg)
+    DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
          << " clobbered, invalidating ";
     if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
       DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
@@ -1135,9 +1135,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
           else
             DOUT << "Reusing SS#" << ReuseSlot;
           DOUT << " from physreg "
-               << TRI->getName(PhysReg) << " for vreg"
+               << TRI->getPrintableName(PhysReg) << " for vreg"
                << VirtReg <<" instead of reloading into physreg "
-               << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
+               << TRI->getPrintableName(VRM.getPhys(VirtReg)) << "\n";
           unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
           MI.getOperand(i).setReg(RReg);
 
@@ -1208,8 +1208,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
             DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
           else
             DOUT << "Reusing SS#" << ReuseSlot;
-          DOUT << " from physreg " << TRI->getName(PhysReg) << " for vreg"
-               << VirtReg
+          DOUT << " from physreg " << TRI->getPrintableName(PhysReg)
+              << " for vreg" << VirtReg
                << " instead of reloading into same physreg.\n";
           unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
           MI.getOperand(i).setReg(RReg);

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index dacc50d71c949fc3c9fff6b5c65a9483f96a23da..31055b2a116f8ed84769a6f4ab6cf76924390aca 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -273,7 +273,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
-      O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+      O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
     else
       assert(0 && "not implemented");
     break;
@@ -393,7 +393,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
   const MachineOperand &MO3 = MI->getOperand(Op+2);
 
   assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
-  O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+  O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
 
   // Print the shift opc.
   O << ", "
@@ -402,7 +402,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
 
   if (MO2.getReg()) {
     assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
-    O << TM.getRegisterInfo()->get(MO2.getReg()).Name;
+    O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
     assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
   } else {
     O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
@@ -419,7 +419,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
     return;
   }
 
-  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
 
   if (!MO2.getReg()) {
     if (ARM_AM::getAM2Offset(MO3.getImm()))  // Don't print +0.
@@ -432,7 +432,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
 
   O << ", "
     << (char)ARM_AM::getAM2Op(MO3.getImm())
-    << TM.getRegisterInfo()->get(MO2.getReg()).Name;
+    << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
   
   if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
     O << ", "
@@ -455,7 +455,7 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
   }
 
   O << (char)ARM_AM::getAM2Op(MO2.getImm())
-    << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+    << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
   
   if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
     O << ", "
@@ -469,12 +469,12 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
   const MachineOperand &MO3 = MI->getOperand(Op+2);
   
   assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
-  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
 
   if (MO2.getReg()) {
     O << ", "
       << (char)ARM_AM::getAM3Op(MO3.getImm())
-      << TM.getRegisterInfo()->get(MO2.getReg()).Name
+      << TM.getRegisterInfo()->get(MO2.getReg()).AsmName
       << "]";
     return;
   }
@@ -492,7 +492,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
 
   if (MO1.getReg()) {
     O << (char)ARM_AM::getAM3Op(MO2.getImm())
-      << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+      << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
     return;
   }
 
@@ -545,13 +545,13 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
     return;
   } else if (Modifier && strcmp(Modifier, "base") == 0) {
     // Used for FSTM{D|S} and LSTM{D|S} operations.
-    O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+    O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
     if (ARM_AM::getAM5WBFlag(MO2.getImm()))
       O << "!";
     return;
   }
   
-  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
   
   if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
     O << ", #"
@@ -570,15 +570,15 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
 
   const MachineOperand &MO1 = MI->getOperand(Op);
   assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
-  O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]";
+  O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
 }
 
 void
 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
   const MachineOperand &MO1 = MI->getOperand(Op);
   const MachineOperand &MO2 = MI->getOperand(Op+1);
-  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
-  O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).Name << "]";
+  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+  O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName << "]";
 }
 
 void
@@ -593,9 +593,9 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
     return;
   }
 
-  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
   if (MO3.getReg())
-    O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).Name;
+    O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
   else if (unsigned ImmOffs = MO2.getImm()) {
     O << ", #" << ImmOffs;
     if (Scale > 1)
@@ -620,7 +620,7 @@ ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
   const MachineOperand &MO1 = MI->getOperand(Op);
   const MachineOperand &MO2 = MI->getOperand(Op+1);
-  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+  O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
   if (unsigned ImmOffs = MO2.getImm())
     O << ", #" << ImmOffs << " * 4";
   O << "]";

diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 067a8efb3ce3998821561a8c5807cfea12cf2d68..a46a64cebd9490e3991072a988c1f011a94cd9e5 100644 (file)
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -77,7 +77,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
   if (MO.getType() == MachineOperand::MO_Register) {
     assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
            "Not physreg??");
-    O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+    O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
   } else if (MO.isImmediate()) {
     O << MO.getImm();
     assert(MO.getImm() < (1 << 30));
@@ -92,7 +92,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
-    O << RI.get(MO.getReg()).Name;
+    O << RI.get(MO.getReg()).AsmName;
     return;
 
   case MachineOperand::MO_Immediate:

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 3481414c7a895ebe72f20c49985a6280a93c017c..b050debb46c9b992e0fd29ab2793f47d7785e970 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -334,6 +334,6 @@ int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 
 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
 {
-  std::string s(RegisterDescriptors[reg].Name);
+  std::string s(RegisterDescriptors[reg].PrintableName);
   return s;
 }

diff --git a/lib/Target/CellSPU/SPUAsmPrinter.cpp b/lib/Target/CellSPU/SPUAsmPrinter.cpp
index b62bf62d3df9df3666e4f6082e0d0293274db98d..d96ec9dac1a05e1ed6b7bdbcc6c31b63fdb6b40c 100644 (file)
--- a/lib/Target/CellSPU/SPUAsmPrinter.cpp
+++ b/lib/Target/CellSPU/SPUAsmPrinter.cpp
@@ -75,14 +75,14 @@ namespace {
       unsigned RegNo = MO.getReg();
       assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
              "Not physreg??");
-      O << TM.getRegisterInfo()->get(RegNo).Name;
+      O << TM.getRegisterInfo()->get(RegNo).AsmName;
     }
 
     void printOperand(const MachineInstr *MI, unsigned OpNo) {
       const MachineOperand &MO = MI->getOperand(OpNo);
       if (MO.isRegister()) {
         assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
-        O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+        O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
       } else if (MO.isImmediate()) {
         O << MO.getImm();
       } else {
@@ -149,7 +149,7 @@ namespace {
       // the value contained in the register.  For this reason, the darwin
       // assembler requires that we print r0 as 0 (no r) when used as the base.
       const MachineOperand &MO = MI->getOperand(OpNo);
-      O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+      O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
       O << ", ";
       printOperand(MI, OpNo+1);
     }

diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index 4efc67276621fefb9edccb94b3353cb8f1b4d596..264329d620fb35d8b8a919c282fa71f85504407c 100644 (file)
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -56,7 +56,7 @@ namespace {
         assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
                "Not physref??");
         //XXX Bug Workaround: See note in Printer::doInitialization about %.
-        O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+        O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
       } else {
         printOp(MO);
       }
@@ -168,7 +168,7 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
   const TargetRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
-    O << RI.get(MO.getReg()).Name;
+    O << RI.get(MO.getReg()).AsmName;
     return;
 
   case MachineOperand::MO_Immediate:

diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 872e51cc88d14e358898afafd1815ce5ccf08ccb..4ad57c9a66bdb86a86e9d7c872b34bc0e21148a1 100644 (file)
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -169,9 +169,9 @@ emitFrameDirective(MachineFunction &MF)
   unsigned stackSize = MF.getFrameInfo()->getStackSize();
 
 
-  O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).Name) 
+  O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).AsmName)
                     << "," << stackSize << ","
-                    << "$" << LowercaseString(RI.get(returnReg).Name) 
+                    << "$" << LowercaseString(RI.get(returnReg).AsmName)
                     << "\n";
 }
 
@@ -365,7 +365,7 @@ printOperand(const MachineInstr *MI, int opNum)
   {
     case MachineOperand::MO_Register:
       if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
-        O << "$" << LowercaseString (RI.get(MO.getReg()).Name);
+        O << "$" << LowercaseString (RI.get(MO.getReg()).AsmName);
       else
         O << "$" << MO.getReg();
       break;

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index acc6570e976d9fa53b60a6c8a35372631b6fc9e2..115e490e9e346924a12836b5f54c3571b2b6cd5a 100644 (file)
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -113,7 +113,7 @@ namespace {
         return;
       }
       
-      const char *RegName = TM.getRegisterInfo()->get(RegNo).Name;
+      const char *RegName = TM.getRegisterInfo()->get(RegNo).AsmName;
       // Linux assembler (Others?) does not take register mnemonics.
       // FIXME - What about special registers used in mfspr/mtspr?
       if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index a64c9855f6dcda21ecff2bb71446a76c09fcdedc..3d55969dd039a17c517a4768b83f568bc7435c0b 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -22,7 +22,7 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
 }
 
 // GP8 - One of the 32 64-bit general-purpose registers
-class GP8<GPR SubReg, string n> : PPCReg<SubReg.Name> {
+class GP8<GPR SubReg, string n> : PPCReg<SubReg.AsmName> {
   field bits<5> Num = SubReg.Num;
   let SubRegs = [SubReg];
   let PrintableName = n;

diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index cbbf4126dd8e2d664acae26c740b5e5f7ade582a..d5b20200e4c1e07df3b3992358e6352d6d3c7ddd 100644 (file)
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -146,7 +146,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
-      O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
+      O << "%" << LowercaseString (RI.get(MO.getReg()).AsmName);
     else
       O << "%reg" << MO.getReg();
     break;

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index c4304351e774d60c23df8ce029656cee7ecc67eb..47efd5eb2b6f46120a7afbdac2c770d40e556e19 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -25,7 +25,7 @@ class RegisterClass; // Forward def
 // in the target machine.  String n will become the "name" of the register.
 class Register<string n> {
   string Namespace = "";
-  string Name = n;
+  string AsmName = n;
   string PrintableName = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in

diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index a6a631bd264cc69bebe5e989191172e92651a546..304e0f7c3463aa9b2912d590f3fc56c5cf20b0b8 100644 (file)
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -229,7 +229,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
                     ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
       Reg = getX86SubSuperRegister(Reg, VT);
     }
-    for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
+    for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
       O << (char)tolower(*Name);
     return;
   }
@@ -575,7 +575,7 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
   }
 
   O << '%';
-  for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
+  for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
     O << (char)tolower(*Name);
   return false;
 }

diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index 64013fcff5690c12b357fc9a3523a9770f4737ce..b753297a940413bb43a56600ff52931c4f7695a1 100644 (file)
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -125,7 +125,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
                       ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
         Reg = getX86SubSuperRegister(Reg, VT);
       }
-      O << RI.get(Reg).Name;
+      O << RI.get(Reg).AsmName;
     } else
       O << "reg" << MO.getReg();
     return;
@@ -271,7 +271,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
     break;
   }
 
-  O << '%' << RI.get(Reg).Name;
+  O << '%' << RI.get(Reg).AsmName;
   return false;
 }
 

diff --git a/lib/Target/X86/X86IntelAsmPrinter.h b/lib/Target/X86/X86IntelAsmPrinter.h
index 8e7a31c92e484d83d40992416dfe699a035fed21..2a10e1c9b71c549cd469d9137d6b9f862f084964 100644 (file)
--- a/lib/Target/X86/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/X86IntelAsmPrinter.h
@@ -43,7 +43,7 @@ struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public X86SharedAsmPrinter {
     if (MO.isRegister()) {
       assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
              "Not physreg??");
-      O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+      O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
     } else {
       printOp(MO, Modifier);
     }

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index abfb5d79d3d99bbff3b9274a670c4cfd9a306c7f..cf41dd271af2a9b578ec51577f64ec56519841c5 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -520,8 +520,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
   for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
     const CodeGenRegister &Reg = Registers[i];
     OS << "    { \"";
-    if (!Reg.TheDef->getValueAsString("Name").empty())
-      OS << Reg.TheDef->getValueAsString("Name");
+    if (!Reg.TheDef->getValueAsString("AsmName").empty())
+      OS << Reg.TheDef->getValueAsString("AsmName");
     else
       OS << Reg.getName();
     OS << "\",\t\"";