Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem

to IntrReadWriteArgMem, as it's for reading as well as writing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td
index 444f514d59beed4dd54b770ab42b4c3d6166e625..ca0b4537b26f49c65a5639641705c81857d99f98 100644 (file)
--- a/include/llvm/Intrinsics.td
+++ b/include/llvm/Intrinsics.td
@@ -19,10 +19,11 @@ include "llvm/CodeGen/ValueTypes.td"
 
 class IntrinsicProperty;
 
-// Intr*Mem - Memory properties.  An intrinsic is allowed to have exactly one of
+// Intr*Mem - Memory properties.  An intrinsic is allowed to have at most one of
 // these properties set.  They are listed from the most aggressive (best to use
 // if correct) to the least aggressive.  If no property is set, the worst case
-// is assumed (IntrWriteMem).
+// is assumed (it may read and write any memory it can get access to and it may
+// have other side effects).
 
 // IntrNoMem - The intrinsic does not access memory or have any other side
 // effects.  It may be CSE'd deleted if dead, etc.
@@ -37,15 +38,11 @@ def IntrReadArgMem : IntrinsicProperty;
 // deleted if dead.
 def IntrReadMem : IntrinsicProperty;
 
-// IntrWriteArgMem - This intrinsic reads and writes only from memory that one
-// of its arguments points to, but may access an unspecified amount.  The reads
-// and writes may be volatile, but except for this it has no other side effects.
-def IntrWriteArgMem : IntrinsicProperty;
-
-// IntrWriteMem - This intrinsic may read or modify unspecified memory or has
-// other side effects.  It cannot be modified by the optimizer.  This is the
-// default if the intrinsic has no other Intr*Mem property.
-def IntrWriteMem : IntrinsicProperty;
+// IntrReadWriteArgMem - This intrinsic reads and writes only from memory that
+// one of its arguments points to, but may access an unspecified amount.  The
+// reads and writes may be volatile, but except for this it has no other side
+// effects.
+def IntrReadWriteArgMem : IntrinsicProperty;
 
 // Commutative - This intrinsic is commutative: X op Y == Y op X.
 def Commutative : IntrinsicProperty;
@@ -190,7 +187,7 @@ def int_gcread  : Intrinsic<[llvm_ptr_ty],
                             [IntrReadArgMem]>;
 def int_gcwrite : Intrinsic<[],
                             [llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty],
-                            [IntrWriteArgMem, NoCapture<1>, NoCapture<2>]>;
+                            [IntrReadWriteArgMem, NoCapture<1>, NoCapture<2>]>;
 
 //===--------------------- Code Generator Intrinsics ----------------------===//
 //
@@ -204,21 +201,19 @@ def int_stacksave     : Intrinsic<[llvm_ptr_ty]>,
 def int_stackrestore  : Intrinsic<[], [llvm_ptr_ty]>,
                         GCCBuiltin<"__builtin_stack_restore">;
 
-// IntrWriteArgMem is more pessimistic than strictly necessary for prefetch,
+// IntrReadWriteArgMem is more pessimistic than strictly necessary for prefetch,
 // however it does conveniently prevent the prefetch from being reordered
 // with respect to nearby accesses to the same memory.
 def int_prefetch      : Intrinsic<[],
                                   [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
-                                  [IntrWriteArgMem, NoCapture<0>]>;
+                                  [IntrReadWriteArgMem, NoCapture<0>]>;
 def int_pcmarker      : Intrinsic<[], [llvm_i32_ty]>;
 
 def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;
 
 // Stack Protector Intrinsic - The stackprotector intrinsic writes the stack
 // guard to the correct place on the stack frame.
-def int_stackprotector : Intrinsic<[],
-                                   [llvm_ptr_ty, llvm_ptrptr_ty],
-                                   [IntrWriteMem]>;
+def int_stackprotector : Intrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;
 
 //===------------------- Standard C Library Intrinsics --------------------===//
 //
@@ -226,15 +221,15 @@ def int_stackprotector : Intrinsic<[],
 def int_memcpy  : Intrinsic<[],
                              [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
                               llvm_i32_ty, llvm_i1_ty],
-                            [IntrWriteArgMem, NoCapture<0>, NoCapture<1>]>;
+                            [IntrReadWriteArgMem, NoCapture<0>, NoCapture<1>]>;
 def int_memmove : Intrinsic<[],
                             [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
                              llvm_i32_ty, llvm_i1_ty],
-                            [IntrWriteArgMem, NoCapture<0>, NoCapture<1>]>;
+                            [IntrReadWriteArgMem, NoCapture<0>, NoCapture<1>]>;
 def int_memset  : Intrinsic<[],
                             [llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty,
                              llvm_i32_ty, llvm_i1_ty],
-                            [IntrWriteArgMem, NoCapture<0>]>;
+                            [IntrReadWriteArgMem, NoCapture<0>]>;
 
 // These functions do not actually read memory, but they are sensitive to the
 // rounding mode.  This needs to be modelled separately; in the meantime
@@ -331,7 +326,7 @@ def int_annotation : Intrinsic<[llvm_anyint_ty],
 //
 def int_init_trampoline : Intrinsic<[llvm_ptr_ty],
                                     [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty],
-                                    [IntrWriteArgMem]>,
+                                    [IntrReadWriteArgMem]>,
                           GCCBuiltin<"__builtin_init_trampoline">;
 
 //===------------------------ Overflow Intrinsics -------------------------===//
@@ -369,79 +364,79 @@ def int_memory_barrier : Intrinsic<[],
 def int_atomic_cmp_swap : Intrinsic<[llvm_anyint_ty],
                                     [LLVMAnyPointerType<LLVMMatchType<0>>,
                                      LLVMMatchType<0>, LLVMMatchType<0>],
-                                    [IntrWriteArgMem, NoCapture<0>]>,
+                                    [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_val_compare_and_swap">;
 def int_atomic_load_add : Intrinsic<[llvm_anyint_ty],
                                     [LLVMAnyPointerType<LLVMMatchType<0>>,
                                      LLVMMatchType<0>],
-                                    [IntrWriteArgMem, NoCapture<0>]>,
+                                    [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_add">;
 def int_atomic_swap     : Intrinsic<[llvm_anyint_ty],
                                     [LLVMAnyPointerType<LLVMMatchType<0>>,
                                      LLVMMatchType<0>],
-                                    [IntrWriteArgMem, NoCapture<0>]>,
+                                    [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_lock_test_and_set">;
 def int_atomic_load_sub : Intrinsic<[llvm_anyint_ty],
                                     [LLVMAnyPointerType<LLVMMatchType<0>>,
                                      LLVMMatchType<0>],
-                                    [IntrWriteArgMem, NoCapture<0>]>,
+                                    [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_sub">;
 def int_atomic_load_and : Intrinsic<[llvm_anyint_ty],
                                     [LLVMAnyPointerType<LLVMMatchType<0>>,
                                      LLVMMatchType<0>],
-                                    [IntrWriteArgMem, NoCapture<0>]>,
+                                    [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_and">;
 def int_atomic_load_or   : Intrinsic<[llvm_anyint_ty],
                                      [LLVMAnyPointerType<LLVMMatchType<0>>,
                                       LLVMMatchType<0>],
-                                     [IntrWriteArgMem, NoCapture<0>]>,
+                                     [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_or">;
 def int_atomic_load_xor : Intrinsic<[llvm_anyint_ty],
                                     [LLVMAnyPointerType<LLVMMatchType<0>>,
                                      LLVMMatchType<0>],
-                                    [IntrWriteArgMem, NoCapture<0>]>,
+                                    [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_xor">;
 def int_atomic_load_nand : Intrinsic<[llvm_anyint_ty],
                                      [LLVMAnyPointerType<LLVMMatchType<0>>,
                                       LLVMMatchType<0>],
-                                     [IntrWriteArgMem, NoCapture<0>]>,
+                                     [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_nand">;
 def int_atomic_load_min  : Intrinsic<[llvm_anyint_ty],
                                      [LLVMAnyPointerType<LLVMMatchType<0>>,
                                       LLVMMatchType<0>],
-                                     [IntrWriteArgMem, NoCapture<0>]>,
+                                     [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_min">;
 def int_atomic_load_max  : Intrinsic<[llvm_anyint_ty],
                                      [LLVMAnyPointerType<LLVMMatchType<0>>,
                                       LLVMMatchType<0>],
-                                     [IntrWriteArgMem, NoCapture<0>]>,
+                                     [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_max">;
 def int_atomic_load_umin : Intrinsic<[llvm_anyint_ty],
                                      [LLVMAnyPointerType<LLVMMatchType<0>>,
                                       LLVMMatchType<0>],
-                                     [IntrWriteArgMem, NoCapture<0>]>,
+                                     [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_umin">;
 def int_atomic_load_umax : Intrinsic<[llvm_anyint_ty],
                                      [LLVMAnyPointerType<LLVMMatchType<0>>,
                                       LLVMMatchType<0>],
-                                     [IntrWriteArgMem, NoCapture<0>]>,
+                                     [IntrReadWriteArgMem, NoCapture<0>]>,
                            GCCBuiltin<"__sync_fetch_and_umax">;
 
 //===------------------------- Memory Use Markers -------------------------===//
 //
 def int_lifetime_start  : Intrinsic<[],
                                     [llvm_i64_ty, llvm_ptr_ty],
-                                    [IntrWriteArgMem, NoCapture<1>]>;
+                                    [IntrReadWriteArgMem, NoCapture<1>]>;
 def int_lifetime_end    : Intrinsic<[],
                                     [llvm_i64_ty, llvm_ptr_ty],
-                                    [IntrWriteArgMem, NoCapture<1>]>;
+                                    [IntrReadWriteArgMem, NoCapture<1>]>;
 def int_invariant_start : Intrinsic<[llvm_descriptor_ty],
                                     [llvm_i64_ty, llvm_ptr_ty],
                                     [IntrReadArgMem, NoCapture<1>]>;
 def int_invariant_end   : Intrinsic<[],
                                     [llvm_descriptor_ty, llvm_i64_ty,
                                      llvm_ptr_ty],
-                                    [IntrWriteArgMem, NoCapture<2>]>;
+                                    [IntrReadWriteArgMem, NoCapture<2>]>;
 
 //===-------------------------- Other Intrinsics --------------------------===//
 //

diff --git a/include/llvm/IntrinsicsARM.td b/include/llvm/IntrinsicsARM.td
index 2589de2c5925d621034e5da70ddb6d4dec5a3703..f4a80bb9cb4a49938440fddd948023c20a7db60c 100644 (file)
--- a/include/llvm/IntrinsicsARM.td
+++ b/include/llvm/IntrinsicsARM.td
@@ -42,7 +42,7 @@ let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
   def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, 
                          Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
   def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, 
-                         Intrinsic<[], [llvm_i32_ty], [IntrWriteMem]>;
+                         Intrinsic<[], [llvm_i32_ty], []>;
   def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
                                     [IntrNoMem]>;
   def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
@@ -375,31 +375,31 @@ let TargetPrefix = "arm" in {
   // Interleaving vector stores from N-element structures.
   def int_arm_neon_vst1 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty],
-                                    [IntrWriteArgMem]>;
+                                    [IntrReadWriteArgMem]>;
   def int_arm_neon_vst2 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty,
-                                     LLVMMatchType<0>], [IntrWriteArgMem]>;
+                                     LLVMMatchType<0>], [IntrReadWriteArgMem]>;
   def int_arm_neon_vst3 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty,
                                      LLVMMatchType<0>, LLVMMatchType<0>],
-                                     [IntrWriteArgMem]>;
+                                     [IntrReadWriteArgMem]>;
   def int_arm_neon_vst4 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty,
                                      LLVMMatchType<0>, LLVMMatchType<0>,
-                                     LLVMMatchType<0>], [IntrWriteArgMem]>;
+                                     LLVMMatchType<0>], [IntrReadWriteArgMem]>;
 
   // Vector store N-element structure from one lane.
   def int_arm_neon_vst2lane : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_anyvector_ty,
                                          LLVMMatchType<0>, llvm_i32_ty],
-                                        [IntrWriteArgMem]>;
+                                        [IntrReadWriteArgMem]>;
   def int_arm_neon_vst3lane : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_anyvector_ty,
                                          LLVMMatchType<0>, LLVMMatchType<0>,
-                                         llvm_i32_ty], [IntrWriteArgMem]>;
+                                         llvm_i32_ty], [IntrReadWriteArgMem]>;
   def int_arm_neon_vst4lane : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_anyvector_ty,
                                          LLVMMatchType<0>, LLVMMatchType<0>,
                                          LLVMMatchType<0>, llvm_i32_ty],
-                                        [IntrWriteArgMem]>;
+                                        [IntrReadWriteArgMem]>;
 }

diff --git a/include/llvm/IntrinsicsPowerPC.td b/include/llvm/IntrinsicsPowerPC.td
index 4e959f337c00f1ce07777f746aef98c94e66c470..da85bfba8631b8c206cf62317f8e1dd109d910d5 100644 (file)
--- a/include/llvm/IntrinsicsPowerPC.td
+++ b/include/llvm/IntrinsicsPowerPC.td
@@ -18,17 +18,17 @@
 // Non-altivec intrinsics.
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // dcba/dcbf/dcbi/dcbst/dcbt/dcbz/dcbzl(PPC970) instructions.
-  def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbf  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbf  : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
   // sync instruction
-  def int_ppc_sync : Intrinsic<[], [], [IntrWriteMem]>;
+  def int_ppc_sync : Intrinsic<[], [], []>;
 }
 
 
@@ -86,31 +86,31 @@ class PowerPC_Vec_WWW_Intrinsic<string GCCIntSuffix>
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // Data Stream Control.
   def int_ppc_altivec_dss : GCCBuiltin<"__builtin_altivec_dss">,
-              Intrinsic<[], [llvm_i32_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_i32_ty], []>;
   def int_ppc_altivec_dssall : GCCBuiltin<"__builtin_altivec_dssall">,
-              Intrinsic<[], [], [IntrWriteMem]>;
+              Intrinsic<[], [], []>;
   def int_ppc_altivec_dst : GCCBuiltin<"__builtin_altivec_dst">,
               Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
-                        [IntrWriteMem]>;
+                        []>;
   def int_ppc_altivec_dstt : GCCBuiltin<"__builtin_altivec_dstt">,
               Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
-                        [IntrWriteMem]>;
+                        []>;
   def int_ppc_altivec_dstst : GCCBuiltin<"__builtin_altivec_dstst">,
               Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
-                        [IntrWriteMem]>;
+                        []>;
   def int_ppc_altivec_dststt : GCCBuiltin<"__builtin_altivec_dststt">,
               Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
-                        [IntrWriteMem]>;
+                        []>;
 
   // VSCR access.
   def int_ppc_altivec_mfvscr : GCCBuiltin<"__builtin_altivec_mfvscr">,
               Intrinsic<[llvm_v8i16_ty], [], [IntrReadMem]>;
   def int_ppc_altivec_mtvscr : GCCBuiltin<"__builtin_altivec_mtvscr">,
-              Intrinsic<[], [llvm_v4i32_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v4i32_ty], []>;
 
 
   // Loads.  These don't map directly to GCC builtins because they represent the
@@ -129,20 +129,15 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // Stores.  These don't map directly to GCC builtins because they represent the
   // source address with a single pointer.
   def int_ppc_altivec_stvx :
-              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
-                        [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], []>;
   def int_ppc_altivec_stvxl :
-              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
-                        [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], []>;
   def int_ppc_altivec_stvebx :
-              Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty],
-                        [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty], []>;
   def int_ppc_altivec_stvehx :
-              Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty],
-                        [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty], []>;
   def int_ppc_altivec_stvewx :
-              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
-                        [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], []>;
 
   // Comparisons setting a vector.
   def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">,

diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td
index 08874b0f0a109d2013d5cdbde90a16397214a233..de6502117c10b898cde2e8acbf5e5f99d5e3b1de 100644 (file)
--- a/include/llvm/IntrinsicsX86.td
+++ b/include/llvm/IntrinsicsX86.td
@@ -143,24 +143,24 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v4f32_ty], [IntrWriteMem]>;
+                         llvm_v4f32_ty], []>;
 }
 
 // Cacheability support ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v4f32_ty], [IntrWriteMem]>;
+                         llvm_v4f32_ty], []>;
   def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
-              Intrinsic<[], [], [IntrWriteMem]>;
+              Intrinsic<[], [], []>;
 }
 
 // Control register.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_stmxcsr :
-              Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_ptr_ty], []>;
   def int_x86_sse_ldmxcsr :
-              Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_ptr_ty], []>;
 }
 
 // Misc.
@@ -459,26 +459,26 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v2f64_ty], [IntrWriteMem]>;
+                         llvm_v2f64_ty], []>;
   def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v16i8_ty], [IntrWriteMem]>;
+                         llvm_v16i8_ty], []>;
   def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v4i32_ty], [IntrWriteMem]>;
+                         llvm_v4i32_ty], []>;
 }
 
 // Cacheability support ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v2i64_ty], [IntrWriteMem]>;
+                         llvm_v2i64_ty], []>;
   def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v2f64_ty], [IntrWriteMem]>;
+                         llvm_v2f64_ty], []>;
   def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_i32_ty], [IntrWriteMem]>;
+                         llvm_i32_ty], []>;
 }
 
 // Misc.
@@ -498,13 +498,13 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
               Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
   def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">,
               Intrinsic<[], [llvm_v16i8_ty,
-                         llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>;
+                         llvm_v16i8_ty, llvm_ptr_ty], []>;
   def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">,
-              Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_ptr_ty], []>;
   def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">,
-              Intrinsic<[], [], [IntrWriteMem]>;
+              Intrinsic<[], [], []>;
   def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">,
-              Intrinsic<[], [], [IntrWriteMem]>;
+              Intrinsic<[], [], []>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -546,10 +546,10 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse3_monitor : GCCBuiltin<"__builtin_ia32_monitor">,
               Intrinsic<[], [llvm_ptr_ty,
-                         llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>;
+                         llvm_i32_ty, llvm_i32_ty], []>;
   def int_x86_sse3_mwait : GCCBuiltin<"__builtin_ia32_mwait">,
               Intrinsic<[], [llvm_i32_ty,
-                         llvm_i32_ty], [IntrWriteMem]>;
+                         llvm_i32_ty], []>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1363,21 +1363,21 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 // SIMD store ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_avx_storeu_pd_256 : GCCBuiltin<"__builtin_ia32_storeupd256">,
-        Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], [IntrWriteMem]>;
+        Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>;
   def int_x86_avx_storeu_ps_256 : GCCBuiltin<"__builtin_ia32_storeups256">,
-        Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], [IntrWriteMem]>;
+        Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>;
   def int_x86_avx_storeu_dq_256 : GCCBuiltin<"__builtin_ia32_storedqu256">,
-        Intrinsic<[], [llvm_ptr_ty, llvm_v32i8_ty], [IntrWriteMem]>;
+        Intrinsic<[], [llvm_ptr_ty, llvm_v32i8_ty], []>;
 }
 
 // Cacheability support ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_avx_movnt_dq_256 : GCCBuiltin<"__builtin_ia32_movntdq256">,
-        Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty], [IntrWriteMem]>;
+        Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty], []>;
   def int_x86_avx_movnt_pd_256 : GCCBuiltin<"__builtin_ia32_movntpd256">,
-        Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], [IntrWriteMem]>;
+        Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>;
   def int_x86_avx_movnt_ps_256 : GCCBuiltin<"__builtin_ia32_movntps256">,
-        Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], [IntrWriteMem]>;
+        Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>;
 }
 
 // Conditional load ops
@@ -1396,18 +1396,18 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_avx_maskstore_pd : GCCBuiltin<"__builtin_ia32_maskstorepd">,
         Intrinsic<[], [llvm_ptr_ty,
-                  llvm_v2f64_ty, llvm_v2f64_ty], [IntrWriteMem]>;
+                  llvm_v2f64_ty, llvm_v2f64_ty], []>;
   def int_x86_avx_maskstore_ps : GCCBuiltin<"__builtin_ia32_maskstoreps">,
         Intrinsic<[], [llvm_ptr_ty,
-                  llvm_v4f32_ty, llvm_v4f32_ty], [IntrWriteMem]>;
+                  llvm_v4f32_ty, llvm_v4f32_ty], []>;
   def int_x86_avx_maskstore_pd_256 :
         GCCBuiltin<"__builtin_ia32_maskstorepd256">,
         Intrinsic<[], [llvm_ptr_ty,
-                  llvm_v4f64_ty, llvm_v4f64_ty], [IntrWriteMem]>;
+                  llvm_v4f64_ty, llvm_v4f64_ty], []>;
   def int_x86_avx_maskstore_ps_256 :
         GCCBuiltin<"__builtin_ia32_maskstoreps256">,
         Intrinsic<[], [llvm_ptr_ty,
-                  llvm_v8f32_ty, llvm_v8f32_ty], [IntrWriteMem]>;
+                  llvm_v8f32_ty, llvm_v8f32_ty], []>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1416,9 +1416,9 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 // Empty MMX state op.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_mmx_emms  : GCCBuiltin<"__builtin_ia32_emms">,
-              Intrinsic<[], [], [IntrWriteMem]>;
+              Intrinsic<[], [], []>;
   def int_x86_mmx_femms : GCCBuiltin<"__builtin_ia32_femms">,
-              Intrinsic<[], [], [IntrWriteMem]>;
+              Intrinsic<[], [], []>;
 }
 
 // Integer arithmetic ops.
@@ -1594,14 +1594,11 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 // Misc.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_mmx_maskmovq : GCCBuiltin<"__builtin_ia32_maskmovq">,
-              Intrinsic<[],
-                        [llvm_v8i8_ty, llvm_v8i8_ty, llvm_ptr_ty],
-                        [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v8i8_ty, llvm_v8i8_ty, llvm_ptr_ty], []>;
 
   def int_x86_mmx_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb">,
               Intrinsic<[llvm_i32_ty], [llvm_v8i8_ty], [IntrNoMem]>;
 
   def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">,
-              Intrinsic<[], [llvm_ptr_ty,
-                         llvm_v1i64_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>;
 }

diff --git a/lib/Target/MBlaze/MBlazeIntrinsics.td b/lib/Target/MBlaze/MBlazeIntrinsics.td
index 82552fa4b343a3987a4e1885808e0ba0bac5b6f0..a27cb5ba0dc4f1e657e0e2e41e6a24841ea9e27e 100644 (file)
--- a/lib/Target/MBlaze/MBlazeIntrinsics.td
+++ b/lib/Target/MBlaze/MBlazeIntrinsics.td
@@ -17,17 +17,11 @@
 
 // MBlaze intrinsic classes.
 let TargetPrefix = "mblaze", isTarget = 1 in { 
-  class MBFSL_Get_Intrinsic : Intrinsic<[llvm_i32_ty],
-                                        [llvm_i32_ty],
-                                        [IntrWriteMem]>;
+  class MBFSL_Get_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;
 
-  class MBFSL_Put_Intrinsic : Intrinsic<[],
-                                        [llvm_i32_ty, llvm_i32_ty],
-                                        [IntrWriteMem]>;
+  class MBFSL_Put_Intrinsic : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
 
-  class MBFSL_PutT_Intrinsic : Intrinsic<[],
-                                         [llvm_i32_ty],
-                                         [IntrWriteMem]>;
+  class MBFSL_PutT_Intrinsic : Intrinsic<[], [llvm_i32_ty], []>;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp
index 878ed09550aaba2e436ba0beeb0f11681a3f553d..303aa6c450c295a8379e6327cf150e3fa937eb8b 100644 (file)
--- a/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -2197,10 +2197,10 @@ private:
       if (IntInfo->ModRef >= CodeGenIntrinsic::ReadArgMem)
         mayLoad = true;// These may load memory.
 
-      if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
+      if (IntInfo->ModRef >= CodeGenIntrinsic::ReadWriteArgMem)
         mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
 
-      if (IntInfo->ModRef >= CodeGenIntrinsic::WriteMem)
+      if (IntInfo->ModRef >= CodeGenIntrinsic::ReadWriteMem)
         // WriteMem intrinsics can have other strange effects.
         HasSideEffects = true;
     }

diff --git a/utils/TableGen/CodeGenIntrinsics.h b/utils/TableGen/CodeGenIntrinsics.h
index 7e7bdf989acf8c17f35cb92300c9a5fde9642341..3208c0d628d96bafc83a7a224a226c19f0373a6f 100644 (file)
--- a/utils/TableGen/CodeGenIntrinsics.h
+++ b/utils/TableGen/CodeGenIntrinsics.h
@@ -60,7 +60,7 @@ namespace llvm {
 
     // Memory mod/ref behavior of this intrinsic.
     enum {
-      NoMem, ReadArgMem, ReadMem, WriteArgMem, WriteMem
+      NoMem, ReadArgMem, ReadMem, ReadWriteArgMem, ReadWriteMem
     } ModRef;
 
     /// This is set to true if the intrinsic is overloaded by its argument

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index 2662fffe4b2c1e6a916b63d000e99822327b6ed6..cbfe2addbf2b73f431b2b2d09d449ad7e925abf2 100644 (file)
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -434,7 +434,7 @@ std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
   TheDef = R;
   std::string DefName = R->getName();
-  ModRef = WriteMem;
+  ModRef = ReadWriteMem;
   isOverloaded = false;
   isCommutative = false;
   
@@ -555,10 +555,8 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
       ModRef = ReadArgMem;
     else if (Property->getName() == "IntrReadMem")
       ModRef = ReadMem;
-    else if (Property->getName() == "IntrWriteArgMem")
-      ModRef = WriteArgMem;
-    else if (Property->getName() == "IntrWriteMem")
-      ModRef = WriteMem;
+    else if (Property->getName() == "IntrReadWriteArgMem")
+      ModRef = ReadWriteArgMem;
     else if (Property->getName() == "Commutative")
       isCommutative = true;
     else if (Property->isSubClassOf("NoCapture")) {

diff --git a/utils/TableGen/IntrinsicEmitter.cpp b/utils/TableGen/IntrinsicEmitter.cpp
index d7a90513df33d8b62563afcd18ad4fc067dd6f46..ba30d97eaa35b4103447a666d0a943fd81b7ee36 100644 (file)
--- a/utils/TableGen/IntrinsicEmitter.cpp
+++ b/utils/TableGen/IntrinsicEmitter.cpp
@@ -545,7 +545,7 @@ EmitModRefBehavior(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS){
   OS << "switch (iid) {\n";
   OS << "default:\n    return UnknownModRefBehavior;\n";
   for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
-    if (Ints[i].ModRef == CodeGenIntrinsic::WriteMem)
+    if (Ints[i].ModRef == CodeGenIntrinsic::ReadWriteMem)
       continue;
     OS << "case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName
       << ":\n";
@@ -559,7 +559,7 @@ EmitModRefBehavior(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS){
     case CodeGenIntrinsic::ReadMem:
       OS << "  return OnlyReadsMemory;\n";
       break;
-    case CodeGenIntrinsic::WriteArgMem:
+    case CodeGenIntrinsic::ReadWriteArgMem:
       OS << "  return AccessesArguments;\n";
       break;
     }