More long double fixes. x86_64 should build now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42155 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/RuntimeLibcalls.h b/include/llvm/CodeGen/RuntimeLibcalls.h
index 2609c55b1512c0795e8a534300e5417393d71614..0b36c6dd28f0cd68eedaf2b31d6cf0bf4c327481 100644 (file)
--- a/include/llvm/CodeGen/RuntimeLibcalls.h
+++ b/include/llvm/CodeGen/RuntimeLibcalls.h
@@ -70,14 +70,18 @@ namespace RTLIB {
     FPTOSINT_F32_I64,
     FPTOSINT_F64_I32,
     FPTOSINT_F64_I64,
+    FPTOSINT_LD_I64,
     FPTOUINT_F32_I32,
     FPTOUINT_F32_I64,
     FPTOUINT_F64_I32,
     FPTOUINT_F64_I64,
+    FPTOUINT_LD_I32,
+    FPTOUINT_LD_I64,
     SINTTOFP_I32_F32,
     SINTTOFP_I32_F64,
     SINTTOFP_I64_F32,
     SINTTOFP_I64_F64,
+    SINTTOFP_I64_LD,
     UINTTOFP_I32_F32,
     UINTTOFP_I32_F64,
     UINTTOFP_I64_F32,

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 10a5f212e0230624507526c4479a10f3772b3d9a..34fca4d6239f932a4620e95d2d51527be1721f95 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3212,8 +3212,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           MVT::ValueType VT =  Node->getOperand(0).getValueType();
           MVT::ValueType NVT = Node->getValueType(0);
           unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
-          Tmp2 = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT),
-                                                 1ULL << ShiftAmt)), VT);
+          const uint64_t zero[] = {0, 0};
+          APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
+          uint64_t x = 1ULL << ShiftAmt;
+          (void)apf.convertFromInteger(&x, 1, false, APFloat::rmTowardZero);
+          Tmp2 = DAG.getConstantFP(apf, VT);
           Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
                             Node->getOperand(0), Tmp2, ISD::SETLT);
           True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
@@ -3235,22 +3238,34 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       MVT::ValueType VT = Op.getValueType();
       RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
       switch (Node->getOpcode()) {
-      case ISD::FP_TO_SINT:
-        if (Node->getOperand(0).getValueType() == MVT::f32)
+      case ISD::FP_TO_SINT: {
+        MVT::ValueType OVT = Node->getOperand(0).getValueType();
+        if (OVT == MVT::f32)
           LC = (VT == MVT::i32)
             ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
-        else
+        else if (OVT == MVT::f64)
           LC = (VT == MVT::i32)
             ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
+        else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
+          assert(VT == MVT::i64);
+          LC = RTLIB::FPTOSINT_LD_I64;
+        }
         break;
-      case ISD::FP_TO_UINT:
-        if (Node->getOperand(0).getValueType() == MVT::f32)
+      }
+      case ISD::FP_TO_UINT: {
+        MVT::ValueType OVT = Node->getOperand(0).getValueType();
+        if (OVT == MVT::f32)
           LC = (VT == MVT::i32)
             ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
-        else
+        else if (OVT == MVT::f64)
           LC = (VT == MVT::i32)
             ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
+        else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
+          LC = (VT == MVT::i32)
+            ? RTLIB::FPTOUINT_LD_I32 : RTLIB::FPTOUINT_LD_I64;
+        }
         break;
+      }
       default: assert(0 && "Unreachable!");
       }
       SDOperand Dummy;
@@ -4767,8 +4782,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   if (DestVT == MVT::f32)
     FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
   else {
-    assert(DestVT == MVT::f64 && "Unexpected conversion");
-    FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
+    FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
                                            DAG.getEntryNode(), CPIdx,
                                            NULL, 0, MVT::f32));
   }
@@ -5350,8 +5364,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     RTLIB::Libcall LC;
     if (Node->getOperand(0).getValueType() == MVT::f32)
       LC = RTLIB::FPTOSINT_F32_I64;
-    else
+    else if (Node->getOperand(0).getValueType() == MVT::f64)
       LC = RTLIB::FPTOSINT_F64_I64;
+    else
+      LC = RTLIB::FPTOSINT_LD_I64;
     Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
                        false/*sign irrelevant*/, Hi);
     break;
@@ -5730,8 +5746,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     if (Node->getOperand(0).getValueType() == MVT::i64) {
       if (VT == MVT::f32)
         LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
-      else
+      else if (VT == MVT::f64)
         LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
+      else if (VT == MVT::f80 || VT == MVT::f128 || VT == MVT::ppcf128) {
+        assert(isSigned);
+        LC = RTLIB::SINTTOFP_I64_LD;
+      }
     } else {
       if (VT == MVT::f32)
         LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3744c4ad663a83bf49646933124a23f6e64e5cab..92c0f2445bcb2c5bd55cec05f892573301671df8 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1591,8 +1591,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     case ISD::ANY_EXTEND:
     case ISD::ZERO_EXTEND: return getConstant(Val, VT);
     case ISD::TRUNCATE:    return getConstant(Val, VT);
-    case ISD::SINT_TO_FP:  return getConstantFP(C->getSignExtended(), VT);
-    case ISD::UINT_TO_FP:  return getConstantFP(C->getValue(), VT);
+    case ISD::UINT_TO_FP:
+    case ISD::SINT_TO_FP: {
+      const uint64_t zero[] = {0, 0};
+      APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
+      (void)apf.convertFromInteger(&Val, 1, Opcode==ISD::SINT_TO_FP,
+                                  APFloat::rmTowardZero);
+      return getConstantFP(apf, VT);
+    }
     case ISD::BIT_CONVERT:
       if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
         return getConstantFP(BitsToFloat(Val), VT);
@@ -1669,8 +1675,12 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     case ISD::FP_EXTEND:
       // This can return overflow, underflow, or inexact; we don't care.
       // FIXME need to be more flexible about rounding mode.
+      // FIXME need to be more flexible about rounding mode.
       (void) V.convert(VT==MVT::f32 ? APFloat::IEEEsingle : 
-                                      APFloat::IEEEdouble,
+                       VT==MVT::f64 ? APFloat::IEEEdouble :
+                       VT==MVT::f80 ? APFloat::x87DoubleExtended :
+                       VT==MVT::f128 ? APFloat::IEEEquad :
+                       APFloat::Bogus,
                        APFloat::rmNearestTiesToEven);
       return getConstantFP(V, VT);
     case ISD::FP_TO_SINT:

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 2dbd4e8c7e4423718458397be1b404605359e61a..4d87ac347a4fee011db09a4a92c747a02c3610fd 100644 (file)
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -69,14 +69,18 @@ static void InitLibcallNames(const char **Names) {
   Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
   Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
   Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
+  Names[RTLIB::FPTOSINT_LD_I64] = "__fixxfdi";
   Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
   Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
   Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
   Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
+  Names[RTLIB::FPTOUINT_LD_I32] = "__fixunsxfsi";
+  Names[RTLIB::FPTOUINT_LD_I64] = "__fixunsxfdi";
   Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
   Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
   Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
   Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
+  Names[RTLIB::SINTTOFP_I64_LD] = "__floatdixf";
   Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
   Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
   Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";

diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td
index 7c555dd46f1a387318489b0aa43fd84afaa2a9a9..9c2d95a19919ad5adb145213f458210ff4b53cfc 100644 (file)
--- a/lib/Target/X86/X86CallingConv.td
+++ b/lib/Target/X86/X86CallingConv.td
@@ -118,8 +118,10 @@ def CC_X86_64_C : CallingConv<[
   // 8-byte aligned if there are no more registers to hold them.
   CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
   
+  // Long doubles get 16-byte stack slots that are 16-byte aligned.
   // Vectors get 16-byte stack slots that are 16-byte aligned.
-  CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
+  CCIfType<[f80, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 
+              CCAssignToStack<16, 16>>,
 
   // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
   CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 3b4b4f91750f28b4c51986858ecff7858b7bb377..bdd424fbfe17d25afbe970d43e0d227c6c7ea2eb 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -108,11 +108,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Custom);
   }
 
-  if (!Subtarget->is64Bit()) {
-    // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
-    setOperationAction(ISD::SINT_TO_FP     , MVT::i64  , Custom);
-    setOperationAction(ISD::FP_TO_SINT     , MVT::i64  , Custom);
-  }
+  // In 32-bit mode these are custom lowered.  In 64-bit mode F32 and F64
+  // are Legal, f80 is custom lowered.
+  setOperationAction(ISD::FP_TO_SINT     , MVT::i64  , Custom);
+  setOperationAction(ISD::SINT_TO_FP     , MVT::i64  , Custom);
 
   // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
   // this operation.
@@ -3343,6 +3342,9 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
   // These are really Legal; caller falls through into that case.
   if (SrcVT==MVT::i32 && Op.getValueType() != MVT::f80 && X86ScalarSSE)
     return Result;
+  if (SrcVT==MVT::i64 && Op.getValueType() != MVT::f80 && 
+      Subtarget->is64Bit())
+    return Result;
 
   // Build the FILD
   SDVTList Tys;
@@ -3397,6 +3399,10 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
   if (Op.getValueType() == MVT::i32 && X86ScalarSSE && 
       Op.getOperand(0).getValueType() != MVT::f80)
     return Result;
+  if (Subtarget->is64Bit() &&
+      Op.getValueType() == MVT::i64 &&
+      Op.getOperand(0).getValueType() != MVT::f80)
+    return Result;
 
   unsigned Opc;
   switch (Op.getValueType()) {