Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6373 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index f6761d03cfe6ee1f80f55c9f6ae88f4850078a34..f66b36f9be4a613812bb6ebc626a499ccd6adfff 100644 (file)
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -309,7 +309,8 @@ private :
   
   unsigned getOperandMask(unsigned Opcode) {
     switch (Opcode) {
-    case V9::SUBcc:   return 1 << 3;  // Remove CC argument
+    case V9::SUBccr:
+    case V9::SUBcci:   return 1 << 3;  // Remove CC argument
   //case BA:      return 1 << 0;  // Remove Arg #0, which is always null or xcc
     default:      return 0;       // By default, don't hack operands...
     }
@@ -320,8 +321,10 @@ inline bool
 SparcFunctionAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
                                                unsigned int opNum) {
   switch (MI->getOpCode()) {
-  case V9::JMPLCALL:
-  case V9::JMPLRET:
+  case V9::JMPLCALLr:
+  case V9::JMPLCALLi:
+  case V9::JMPLRETr:
+  case V9::JMPLRETi:
     return (opNum == 0);
   default:
     return false;

diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index aa48278fbff6441fde3140d91eb81d06c873be67..5111246073ecef56ceff50bb8b355f1e393382f5 100644 (file)
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -108,12 +108,12 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
   if (miSETHI==NULL || C & MAXLO) {
     if (miSETHI) {
       // unsigned value with high-order bits set using SETHI
-      miOR = BuildMI(V9::OR,3).addReg(dest).addZImm(C).addRegDef(dest);
+      miOR = BuildMI(V9::ORi,3).addReg(dest).addZImm(C).addRegDef(dest);
       miOR->setOperandLo32(1);
     } else {
       // unsigned or small signed value that fits in simm13 field of OR
       assert(smallNegValue || (C & ~MAXSIMM) == 0);
-      miOR = BuildMI(V9::OR, 3).addMReg(target.getRegInfo()
+      miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()
                                         .getZeroRegNum())
         .addSImm(sC).addRegDef(dest);
     }
@@ -145,7 +145,7 @@ CreateSETSWConst(const TargetMachine& target, int32_t C,
   // Sign-extend to the high 32 bits if needed.
   // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
   if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
-    mvec.push_back(BuildMI(V9::SRA, 3).addReg(dest).addZImm(0).addRegDef(dest));
+    mvec.push_back(BuildMI(V9::SRAi6, 3).addReg(dest).addZImm(0).addRegDef(dest));
 }
 
 
@@ -172,14 +172,14 @@ CreateSETXConst(const TargetMachine& target, uint64_t C,
   CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
   
   // Shift tmpReg left by 32 bits
-  mvec.push_back(BuildMI(V9::SLLX, 3).addReg(tmpReg).addZImm(32)
+  mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
                  .addRegDef(tmpReg));
   
   // Code to set the low 32 bits of the value in register `dest'
   CreateSETUWConst(target, C, dest, mvec);
   
   // dest = OR(tmpReg, dest)
-  mvec.push_back(BuildMI(V9::OR,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
+  mvec.push_back(BuildMI(V9::ORr,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
 }
 
 
@@ -201,7 +201,7 @@ CreateSETUWLabel(const TargetMachine& target, Value* val,
   mvec.push_back(MI);
   
   // Set the low 10 bits in dest
-  MI = BuildMI(V9::OR, 3).addReg(dest).addReg(val).addRegDef(dest);
+  MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(val).addRegDef(dest);
   MI->setOperandLo32(1);
   mvec.push_back(MI);
 }
@@ -227,20 +227,20 @@ CreateSETXLabel(const TargetMachine& target,
   MI->setOperandHi64(0);
   mvec.push_back(MI);
   
-  MI = BuildMI(V9::OR, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
+  MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
   MI->setOperandLo64(1);
   mvec.push_back(MI);
   
-  mvec.push_back(BuildMI(V9::SLLX, 3).addReg(tmpReg).addZImm(32)
+  mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
                  .addRegDef(tmpReg));
   MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest);
   MI->setOperandHi32(0);
   mvec.push_back(MI);
   
-  MI = BuildMI(V9::OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
+  MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
   mvec.push_back(MI);
   
-  MI = BuildMI(V9::OR, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
+  MI = BuildMI(V9::ORi, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
   MI->setOperandLo32(1);
   mvec.push_back(MI);
 }
@@ -311,20 +311,20 @@ MaxConstantForInstr(unsigned llvmOpCode)
 
   if (llvmOpCode >= Instruction::BinaryOpsBegin &&
       llvmOpCode <  Instruction::BinaryOpsEnd)
-    modelOpCode = V9::ADD;
+    modelOpCode = V9::ADDi;
   else
     switch(llvmOpCode) {
-    case Instruction::Ret:   modelOpCode = V9::JMPLCALL; break;
+    case Instruction::Ret:   modelOpCode = V9::JMPLCALLi; break;
 
     case Instruction::Malloc:         
     case Instruction::Alloca:         
     case Instruction::GetElementPtr:  
     case Instruction::PHINode:       
     case Instruction::Cast:
-    case Instruction::Call:  modelOpCode = V9::ADD; break;
+    case Instruction::Call:  modelOpCode = V9::ADDi; break;
 
     case Instruction::Shl:
-    case Instruction::Shr:   modelOpCode = V9::SLLX; break;
+    case Instruction::Shr:   modelOpCode = V9::SLLXi6; break;
 
     default: break;
     };
@@ -673,12 +673,12 @@ CreateBitExtensionInstructions(bool signExtend,
     TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
                                               srcVal, destVal, "make32");
     mcfi.addTemp(tmpI);
-    mvec.push_back(BuildMI(V9::SLLX, 3).addReg(srcVal)
+    mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(srcVal)
                    .addZImm(32-numLowBits).addRegDef(tmpI));
     srcVal = tmpI;
   }
 
-  mvec.push_back(BuildMI(signExtend? V9::SRA : V9::SRL, 3)
+  mvec.push_back(BuildMI(signExtend? V9::SRAi6 : V9::SRLi6, 3)
                  .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
 }
 

diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index 532a178a33baaa477a911baa4dc32d2dbbd886dc..5aa74f36052c37a23641cac0e677f816adb1020d 100644 (file)
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -63,9 +63,9 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
   
   int32_t C = - (int) staticStackSize;
   int SP = TM.getRegInfo().getStackPointer();
-  if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVE,staticStackSize)) {
-    mvec.push_back(BuildMI(V9::SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP,
-                                                                    MOTy::Def));
+  if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
+    mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
+                   .addMReg(SP, MOTy::Def));
   } else {
     // We have to put the stack size value into a register before SAVE.
     // Use register %g1 since it is volatile across calls.  Note that the
@@ -81,17 +81,17 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
     M->setOperandHi32(0);
     mvec.push_back(M);
     
-    M = BuildMI(V9::OR, 3).addMReg(uregNum).addSImm(C)
+    M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
       .addMReg(uregNum, MOTy::Def);
     M->setOperandLo32(1);
     mvec.push_back(M);
     
-    M = BuildMI(V9::SRA, 3).addMReg(uregNum).addZImm(0)
+    M = BuildMI(V9::SRAi6, 3).addMReg(uregNum).addZImm(0)
       .addMReg(uregNum, MOTy::Def);
     mvec.push_back(M);
     
     // Now generate the SAVE using the value in register %g1
-    M = BuildMI(V9::SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP,MOTy::Def);
+    M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum).addMReg(SP,MOTy::Def);
     mvec.push_back(M);
   }
 
@@ -116,7 +116,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
       int nextArgOffset = firstArgOffset + numFixedArgs * argSize;
 
       for (int i=numFixedArgs; i < numArgRegs; ++i) {
-        mvec.push_back(BuildMI(V9::STX, 3).addMReg(firstArgReg+i).
+        mvec.push_back(BuildMI(V9::STXi, 3).addMReg(firstArgReg+i).
                        addMReg(fpReg).addSImm(nextArgOffset));
         nextArgOffset += argSize;
       }
@@ -139,7 +139,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
     {
       int ZR = TM.getRegInfo().getZeroRegNum();
       MachineInstr *Restore = 
-        BuildMI(V9::RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
+        BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
       
       MachineCodeForInstruction &termMvec =
         MachineCodeForInstruction::get(TermInst);