LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar
8489376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047
91177308-0d34-0410-b5e6-
96231b3b80d8
unsigned Align = (*Op0->memoperands_begin())->getAlignment();
const Function *Func = MF->getFunction();
unsigned ReqAlign = STI->hasV6Ops()
- ? TD->getPrefTypeAlignment(Type::getInt64Ty(Func->getContext()))
+ ? TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext()))
: 8; // Pre-v6 need 8-byte align
if (Align < ReqAlign)
return false;
std::string getDataLayout() const {
if (isThumb()) {
if (isAPCS_ABI()) {
- return std::string("e-p:32:32-f64:32:32-i64:32:32-"
+ return std::string("e-p:32:32-f64:32:64-i64:32:64-"
"i16:16:32-i8:8:32-i1:8:32-"
"v128:32:128-v64:32:64-a:0:32-n32");
} else {
}
} else {
if (isAPCS_ABI()) {
- return std::string("e-p:32:32-f64:32:32-i64:32:32-"
+ return std::string("e-p:32:32-f64:32:64-i64:32:64-"
"v128:32:128-v64:32:64-n32");
} else {
return std::string("e-p:32:32-f64:64:64-i64:64:64-"
@e = global i64 4
;ELF: .align 3
;ELF: e
-;DARWIN: .align 2
+;DARWIN: .align 3
;DARWIN: _e:
@f = global float 5.0
@g = global double 6.0
;ELF: .align 3
;ELF: g:
-;DARWIN: .align 2
+;DARWIN: .align 3
;DARWIN: _g:
@bar = common global [75 x i8] zeroinitializer, align 128