Use pseudo instructions for VST1d64Q.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index c71b093b0b6bb40854843ae7a2c3d794fd8e3ea1..56c6468bb4373bb77fa005bbf85062468d45a0f9 100644 (file)
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -229,12 +229,16 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
       ExpandVST4(MBBI, ARM::VST4d16, false, SingleSpc); break;
     case ARM::VST4d32Pseudo:
       ExpandVST4(MBBI, ARM::VST4d32, false, SingleSpc); break;
+    case ARM::VST1d64QPseudo:
+      ExpandVST4(MBBI, ARM::VST1d64Q, false, SingleSpc); break;
     case ARM::VST4d8Pseudo_UPD:
       ExpandVST4(MBBI, ARM::VST4d8_UPD, true, SingleSpc); break;
     case ARM::VST4d16Pseudo_UPD:
       ExpandVST4(MBBI, ARM::VST4d16_UPD, true, SingleSpc); break;
     case ARM::VST4d32Pseudo_UPD:
       ExpandVST4(MBBI, ARM::VST4d32_UPD, true, SingleSpc); break;
+    case ARM::VST1d64QPseudo_UPD:
+      ExpandVST4(MBBI, ARM::VST1d64Q_UPD, true, SingleSpc); break;
     case ARM::VST4q8Pseudo_UPD:
       ExpandVST4(MBBI, ARM::VST4q8_UPD, true, EvenDblSpc); break;
     case ARM::VST4q16Pseudo_UPD:

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 86f64bc48a04a874728487e217aa545f7350a753..3619084b356a183eaf5a6aebd4f666a22994bcfe 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1262,8 +1262,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
 
   // FIXME: This is a temporary flag to distinguish VSTs that have been
   // converted to pseudo instructions.
-  bool usePseudoInstrs = (NumVecs == 4 &&
-                          VT.getSimpleVT().SimpleTy != MVT::v1i64);
+  bool usePseudoInstrs = (NumVecs == 4);
 
   if (is64BitVector) {
     if (NumVecs >= 2) {
@@ -2331,7 +2330,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
 
     case Intrinsic::arm_neon_vst4: {
       unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
-                              ARM::VST4d32Pseudo, ARM::VST1d64Q };
+                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
       unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
                                ARM::VST4q16Pseudo_UPD,
                                ARM::VST4q32Pseudo_UPD };

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 4c14b233148092b9db916d874a6856f385709565..cf697b2cdc956c7001ca4454fdab028adfa6072b 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -583,6 +583,9 @@ def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
 
+def VST1d64QPseudo     : VSTQQPseudo;
+def VST1d64QPseudo_UPD : VSTQQWBPseudo;
+
 //   VST2     : Vector Store (multiple 2-element structures)
 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
   : NLdSt<0, 0b00, op11_8, op7_4, (outs),

diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp
index 0c1cfaead35ef2db412f3429d8e5ea5518ce21d5..143999531a3978a3c58514c2b5cd32365b1a744d 100644 (file)
--- a/lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/lib/Target/ARM/NEONPreAllocPass.cpp
@@ -260,7 +260,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
     Stride = 2;
     return true;
 
-  case ARM::VST1d64Q:
   case ARM::VST4LNd8:
   case ARM::VST4LNd16:
   case ARM::VST4LNd32: