Merge tag 'v3.20-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorOlof Johansson <olof@lixom.net>
Fri, 6 Feb 2015 08:03:28 +0000 (00:03 -0800)
committerOlof Johansson <olof@lixom.net>
Fri, 6 Feb 2015 08:03:28 +0000 (00:03 -0800)
Merge "ARM: rockchip: third (and last) batch of dts updates for 3.20" from
Heiko Stübner:

Change are regulator nodes for the cpu and gpu regulators on the act8846
variant of the rk3288-evb and the setting of a clock for the watchdog.
Also the lcd and hdmi controllers on both the firefly and the evb get
enabled and let us now boot into fbcon console sucessfully.

* tag 'v3.20-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards
  ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb
  ARM: dts: rockchip: housekeeping off i2c0 on rk3288-evb boards
  ARM: dts: rockchip: add cpu and gpu regulators to rk3288-evb-act8846
  ARM: dts: rockchip: add rk3288 watchdog clock
  clk: rockchip: add id for watchdog pclk on rk3288
  clk: rockchip: add clock IDs for the PVTM clocks
  clk: rockchip: add clock ID for usbphy480m_src

Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm/boot/dts/rk3288-evb-act8846.dts
arch/arm/boot/dts/rk3288-evb-rk808.dts
arch/arm/boot/dts/rk3288-evb.dtsi
arch/arm/boot/dts/rk3288-firefly.dtsi
arch/arm/boot/dts/rk3288.dtsi
include/dt-bindings/clock/rk3288-cru.h

index a76dd44adb533c608bbb892a7e1ba3bcde9de790..d7b8bbc0c25fa00c8ccf59ee0b1ad03485136622 100644 (file)
        compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
 };
 
+&cpu0 {
+       cpu0-supply = <&vdd_cpu>;
+};
+
 &i2c0 {
+       clock-frequency = <400000>;
+
+       vdd_cpu: syr827@40 {
+               compatible = "silergy,syr827";
+               fcs,suspend-voltage-selector = <1>;
+               reg = <0x40>;
+               regulator-name = "vdd_cpu";
+               regulator-min-microvolt = <850000>;
+               regulator-max-microvolt = <1350000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vdd_gpu: syr828@41 {
+               compatible = "silergy,syr828";
+               fcs,suspend-voltage-selector = <1>;
+               reg = <0x41>;
+               regulator-name = "vdd_gpu";
+               regulator-min-microvolt = <850000>;
+               regulator-max-microvolt = <1350000>;
+               regulator-always-on;
+       };
+
        hym8563@51 {
                compatible = "haoyu,hym8563";
                reg = <0x51>;
index d453ddd4b476bb1bc09127ab17ca2acba4fc1eb6..3f7aa9e2e76ade8f5b13d1bc2587ebe5e85d1edc 100644 (file)
@@ -23,7 +23,6 @@
 
 &i2c0 {
        clock-frequency = <400000>;
-       status = "okay";
 
        rk808: pmic@1b {
                compatible = "rockchip,rk808";
index 3e067dd65d0c87d7845809bd121859f86de1a879..86ede5893ab6d2b65f43aa69f6b154e4132ce721 100644 (file)
        status = "okay";
 };
 
+&hdmi {
+       ddc-i2c-bus = <&i2c5>;
+       status = "okay";
+};
+
 &sdmmc {
        bus-width = <4>;
        cap-mmc-highspeed;
        status = "okay";
 };
 
+&i2c5 {
+       status = "okay";
+};
+
 &wdt {
        status = "okay";
 };
 &usb_host1 {
        status = "okay";
 };
+
+&vopb {
+       status = "okay";
+};
+
+&vopb_mmu {
+       status = "okay";
+};
+
+&vopl {
+       status = "okay";
+};
+
+&vopl_mmu {
+       status = "okay";
+};
index 7f0ba9b248692459a9b24552fcaeb3682790f5e0..e6f873abbe0dd991fcdcf5a81dbe33c09aec1e1d 100644 (file)
        status = "okay";
 };
 
+&hdmi {
+       ddc-i2c-bus = <&i2c5>;
+       status = "okay";
+};
+
 &i2c0 {
        clock-frequency = <400000>;
        status = "okay";
                                regulator-name = "vdd10_lcd";
                                regulator-min-microvolt = <1000000>;
                                regulator-max-microvolt = <1000000>;
+                               regulator-always-on;
                        };
 
                        vcca_18: REG7 {
                                regulator-name = "vcc18_lcd";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
                        };
                };
        };
        status = "okay";
 };
 
+&vopb {
+       status = "okay";
+};
+
+&vopb_mmu {
+       status = "okay";
+};
+
+&vopl {
+       status = "okay";
+};
+
+&vopl_mmu {
+       status = "okay";
+};
+
 &wdt {
        status = "okay";
 };
index 37847c14b449655ec93cc6a4712b27bfcffbebdc..1141850d0acb998a04dfbffb14fb75f03cb546d8 100644 (file)
        wdt: watchdog@ff800000 {
                compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
                reg = <0xff800000 0x100>;
+               clocks = <&cru PCLK_WDT>;
                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
                compatible = "rockchip,rk3288-dw-hdmi";
                reg = <0xff980000 0x20000>;
                reg-io-width = <4>;
-               ddc-i2c-bus = <&i2c5>;
                rockchip,grf = <&grf>;
                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
index f60ce72a2b2c76c23da6fa52c7eb470d39195633..1e626335acf3d66ade8596e37921264138e4b9a1 100644 (file)
@@ -80,6 +80,9 @@
 #define SCLK_SDIO0_SAMPLE      119
 #define SCLK_SDIO1_SAMPLE      120
 #define SCLK_EMMC_SAMPLE       121
+#define SCLK_USBPHY480M_SRC    122
+#define SCLK_PVTM_CORE         123
+#define SCLK_PVTM_GPU          124
 
 #define DCLK_VOP0              190
 #define DCLK_VOP1              191
 #define PCLK_PUBL0             365
 #define PCLK_DDRUPCTL1         366
 #define PCLK_PUBL1             367
+#define PCLK_WDT               368
 
 /* hclk gates */
 #define HCLK_GPS               448