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Fixup PPC440 load/store operand latencies
authorHal Finkel <hfinkel@anl.gov>
Fri, 29 Nov 2013 06:19:43 +0000 (06:19 +0000)
committerHal Finkel <hfinkel@anl.gov>
Fri, 29 Nov 2013 06:19:43 +0000 (06:19 +0000)
The operand latencies for loads and stores in the PPC440 itinerary were wrong
(the store operands are all inputs, and the "with update" (pre-increment)
instructions need a latency for the additional output).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195948 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCSchedule440.td patch | blob | history

diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td
index c8e620dd2ddca961f6090029517a117a1df47e9e..11d79f2be01c9335663accd0d71ebeb84c636d6f 100644 (file)
--- a/lib/Target/PowerPC/PPCSchedule440.td
+++ b/lib/Target/PowerPC/PPCSchedule440.td
@@ -228,70 +228,70 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStDCBF,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStDCBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLoad,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [5, 1],
+                                [5, 1, 1],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [5, 1],
+                                [5, 2, 1, 1],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStStore,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStICBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTFD,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1, 1],
+                                [1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTFDU,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1, 1],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLFD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
@@ -305,28 +305,28 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [5, 1, 1],
+                                [5, 2, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLHA,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLHAU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLMW,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLWARX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -335,21 +335,21 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTDU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTDCX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -358,7 +358,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTWCX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -367,7 +367,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSync,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
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