Add new getOperandType(i) method to MachineInstr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4330 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 0b5ceaf272c81101a63e4f7ff566c6baf18ec9c3..ba901a8d743c40f9cb23b26e71d873e46155e0f1 100644 (file)
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -238,14 +238,6 @@ public:
   // 
   unsigned getNumOperands() const { return operands.size(); }
   
-  bool operandIsDefined(unsigned i) const {
-    return getOperand(i).opIsDef();
-  }
-
-  bool operandIsDefinedAndUsed(unsigned i) const {
-    return getOperand(i).opIsDefAndUse();
-  }
-  
   const MachineOperand& getOperand(unsigned i) const {
     assert(i < operands.size() && "getOperand() out of range!");
     return operands[i];
@@ -254,6 +246,18 @@ public:
     assert(i < operands.size() && "getOperand() out of range!");
     return operands[i];
   }
+
+  MachineOperand::MachineOperandType getOperandType(unsigned i) const {
+    return getOperand(i).getOperandType();
+  }
+
+  bool operandIsDefined(unsigned i) const {
+    return getOperand(i).opIsDef();
+  }
+
+  bool operandIsDefinedAndUsed(unsigned i) const {
+    return getOperand(i).opIsDefAndUse();
+  }
   
   //
   // Information about implicit operands of the instruction
@@ -339,7 +343,7 @@ public:
   // physical register after register allocation is complete.
   // 
   void SetRegForOperand(unsigned i, int regNum);
-  
+
   //
   // Iterator to enumerate machine operands.
   // 
@@ -348,10 +352,10 @@ public:
     unsigned i;
     MITy MI;
     
-    inline void skipToNextVal() {
+    void skipToNextVal() {
       while (i < MI->getNumOperands() &&
-             !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
-                MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
+             !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
+                MI->getOperandType(i) == MachineOperand::MO_CCRegister)
                && MI->getOperand(i).getVRegValue() != 0))
         ++i;
     }