UPSTREAM: ARM: dts: rockchip: add to support emac for rk3036 SoCs

This patch adds the emac device node for rk3036 SoCs.
We need to let mac clock under the DPLL which is able to provide
the accurate 50MHz what mac_ref need, since that will cause some
unstable things if the cpufreq is working.

Change-Id: Ie6fdbcda7d45cccbc23e1554141cc3c73b554818
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from git.kernel.org next/linux-next.git master
 commit af671e7bd96bc9bde623b0e6f75bfa4269c2c57f)

diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
index 28a03366601750bc9c2c5a25255e3ba433758bb3..b3d6ec87f6152b1e23c0845913990da1c19076a8 100644 (file)
--- a/arch/arm/boot/dts/rk3036-evb.dts
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -47,6 +47,20 @@
        compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
 };
 
+&emac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+       phy = <&phy0>;
+       phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+       phy-reset-duration = <10>; /* millisecond */
+
+       status = "okay";
+
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
 &i2c1 {
        status = "okay";
 

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index d5913fe128eed0e7b39a8a8ff650bf73f57b63ac..6251d109eff42de9cc5c8ec1784a003fe1eab1c0 100644 (file)
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -112,6 +112,20 @@
        status = "okay";
 };
 
+&emac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+       phy = <&phy0>;
+       phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+       phy-reset-duration = <10>; /* millisecond */
+
+       status = "okay";
+
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
 &emmc {
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 28fa2f848df8933d15bf946d2069353d4e3e4e2b..bd684d1dc6b1444b799d18e17bd20fce03ad56a9 100644 (file)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -187,6 +187,27 @@
                status = "disabled";
        };
 
+       emac: ethernet@10200000 {
+               compatible = "rockchip,rk3036-emac", "snps,arc-emac";
+               reg = <0x10200000 0x4000>;
+               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               rockchip,grf = <&grf>;
+               clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
+               clock-names = "hclk", "macref", "macclk";
+               /*
+                * Fix the emac parent clock is DPLL instead of APLL.
+                * since that will cause some unstable things if the cpufreq
+                * is working. (e.g: the accurate 50MHz what mac_ref need)
+                */
+               assigned-clocks = <&cru SCLK_MACPLL>;
+               assigned-clock-parents = <&cru PLL_DPLL>;
+               max-speed = <100>;
+               phy-mode = "rmii";
+               status = "disabled";
+       };
+
        sdmmc: dwmmc@10214000 {
                compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x10214000 0x4000>;
@@ -572,6 +593,24 @@
                        };
                };
 
+               emac {
+                       emac_xfer: emac-xfer {
+                               rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
+                                               <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
+                                               <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
+                                               <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
+                                               <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
+                                               <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
+                                               <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
+                                               <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
+                       };
+
+                       emac_mdio: emac-mdio {
+                               rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
+                                               <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
+                       };
+               };
+
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
                                rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,