Add RR forms of test instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6509 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.def b/lib/Target/X86/X86InstrInfo.def
index 0ee1a98f8321451a9dc4f0529523be5118fa584b..03c893ba118e7d206a6d2028ee6af24cb42b1e78 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.def
+++ b/lib/Target/X86/X86InstrInfo.def
@@ -188,6 +188,10 @@ I(TESTri8     , "test",  0xF6, 0, X86II::MRMS0r | X86II::Arg8,  NoIR, NoIR)
 I(TESTri16    , "test",  0xF7, 0, X86II::MRMS0r | X86II::Arg16 | X86II::OpSize, NoIR, NoIR)  // flags = R16 & imm16
 I(TESTri32    , "test",  0xF7, 0, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR)                  // flags = R32 & imm32
 
+I(TESTrr8     , "test",  0x84, 0, X86II::MRMDestReg | X86II::Arg8,  NoIR, NoIR)                  // flags = R8 & R8
+I(TESTrr16    , "test",  0x85, 0, X86II::MRMDestReg | X86II::Arg16 | X86II::OpSize, NoIR, NoIR)  // flags = R16 & R16
+I(TESTrr32    , "test",  0x85, 0, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR)                  // flags = R32 & R32
+
 
 // Shift instructions
 I(SHLrr8      , "shl",  0xD2, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR)                                   // R8   <<= cl