thermal: exynos: remove needless threshold_temp abstraction
authorBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thu, 13 Nov 2014 15:00:58 +0000 (16:00 +0100)
committerEduardo Valentin <edubezval@gmail.com>
Thu, 20 Nov 2014 14:52:29 +0000 (10:52 -0400)
reg->threshold_temp is used only in exynos_tmu_initialize() and
is accessed only on Exynos4210 (other SoC types don't even have
threshold_temp entry assigned in their struct exynos_tmu_registers
instances) so the register abstraction is not needed and can be
removed.

There should be no functional changes caused by this patch.

Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
drivers/thermal/samsung/exynos_tmu.c
drivers/thermal/samsung/exynos_tmu.h
drivers/thermal/samsung/exynos_tmu_data.c

index ac436379d9ce708c3b15495494ee55cb8885792b..12e6f16d75c7d4e846eab66b58192f60fbc05ec7 100644 (file)
@@ -219,7 +219,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
                /* Write temperature code for threshold */
                threshold_code = temp_to_code(data, pdata->threshold);
                writeb(threshold_code,
-                       data->base + reg->threshold_temp);
+                       data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
                for (i = 0; i < pdata->non_hw_trigger_levels; i++)
                        writeb(pdata->trigger_levels[i], data->base +
                        reg->threshold_th0 + i * sizeof(reg->threshold_th0));
index 7849d8f2128c16a3ad1250040bc8356cd1147034..d69321579140d1d6669ee88056482cd142c1f3cf 100644 (file)
@@ -84,7 +84,6 @@ enum soc_type {
  * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
  * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
  * @tmu_cur_temp: register containing the current temperature of the TMU.
- * @threshold_temp: register containing the base threshold level.
  * @threshold_th0: Register containing first set of rising levels.
  * @threshold_th1: Register containing second set of rising levels.
  * @threshold_th2: Register containing third set of rising levels.
@@ -116,8 +115,6 @@ struct exynos_tmu_registers {
 
        u32     tmu_cur_temp;
 
-       u32     threshold_temp;
-
        u32     threshold_th0;
        u32     threshold_th1;
        u32     threshold_th2;
index 49c814299bd965f078716921d4e6a2f4a654b416..8153c41b972579a1cf1457febf6a0674040c840a 100644 (file)
@@ -28,7 +28,6 @@
 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
        .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
        .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
-       .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
        .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
        .tmu_inten = EXYNOS_TMU_REG_INTEN,
        .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,