RK292X:modify DDR3 DLL disable frequency,part of the LVDDR3 can not

    work with low-frequency.

diff --git a/arch/arm/mach-rk2928/ddr.c b/arch/arm/mach-rk2928/ddr.c
index 99c9c794c34b8698ea7ba001eb77413e3f43107f..ba874cb654fb298af32b92bed9c6d64cb79ce3ba 100755 (executable)
--- a/arch/arm/mach-rk2928/ddr.c
+++ b/arch/arm/mach-rk2928/ddr.c
@@ -26,7 +26,7 @@
 typedef uint32_t uint32 ;
 
 
-#define DDR3_DDR2_DLL_DISABLE_FREQ    (125)   //lvddr3 ƵÂÊÌ«µÍʱdll²»ÄÜÕý³£¹¤×÷
+#define DDR3_DDR2_DLL_DISABLE_FREQ    (300)
 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)
 #define SR_IDLE                       (0x1)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
 #define PD_IDLE                       (0x40)  //unit:DDR clk cycle, and 0 for disable auto power-down
@@ -1187,8 +1187,16 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
         {
             tmp = 3;
         }
-        cl = ddr3_cl_cwl[ddr_speed_bin][tmp] >> 16;
-        cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0x0ff;
+        if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ)       //when dll bypss cl = cwl = 6;
+        {
+            cl = 6;
+            cwl = 6;
+        }
+        else
+        {
+            cl = ddr3_cl_cwl[ddr_speed_bin][tmp] >> 16;
+            cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0x0ff;
+        }
         if(cl == 0)
         {
             ret = -4; //³¬¹ý¿ÅÁ£µÄ×î´óƵÂÊ