Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.

Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 8c89505a20fe49696f171ba3f1588d64d998cc3a..509a01949d5b2414edd681861b4d7310c7c497c9 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -547,7 +547,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
     return false;
   case ARM::SMLAL:   case ARM::SMULL:   case ARM::UMAAL:   case ARM::UMLAL:
   case ARM::UMULL:   case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB:
-  case ARM::SMLALTT: case ARM::SMLSLD:
+  case ARM::SMLALTT: case ARM::SMLSLD:  case ARM::SMLSLDX:
     if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
       return true;
     if (R19_16 == R15_12)
@@ -1201,12 +1201,8 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
     }
     OpIdx += 1;
   } else {
-    // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of
-    // A8.6.86 LDRT.  So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1,
-    // we should reject this insn as invalid.
-    //
-    // Ditto for LDRBT.
-    if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1))
+    // If Inst{25} = 1 and Inst{4} != 0, we should reject this as invalid.
+    if (slice(insn,4,4) == 1)
       return false;
 
     // Disassemble the offset reg (Rm), shift type, and immediate shift length.

diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index 3dabb7a808327e9f989d475ed332fc3bfea2e657..e235d51896860b69678673e6034a652249f20a4d 100644 (file)
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -198,7 +198,7 @@
 0xa5 0xba 0xd2 0xed
 
 # CHECK:       strtvc  r5, [r3], r0, lsr #20
-0x30 0x5a 0xa3 0x76
+0x20 0x5a 0xa3 0x76
 
 # CHECK:       stmiblo sp, {r0, r4, r8, r11, r12, pc}
 0x11 0x99 0x8d 0x39
@@ -242,3 +242,6 @@
 
 # CHECK:       mrchs   p2, #3, r11, c13, c6, #6
 0xd6 0xb2 0x7d 0x2e
+
+# CHECK:       smlsldx r4, r12, r11, r4
+0x7b 0x44 0x4c 0xe7