initial support for branches

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index adf444d29a671f4626b29feedd0ab88aa262baf3..dbd9bd885987fc552b4131dd91a70da2782f788d 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -174,8 +174,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
     O << "#" << (int)MO.getImmedValue();
     break;
   case MachineOperand::MO_MachineBasicBlock:
-    assert(0 && "not implemented");
-    abort();
+    printBasicBlockLabel(MO.getMachineBasicBlock());
     return;
   case MachineOperand::MO_GlobalAddress: {
     GlobalValue *GV = MO.getGlobal();

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index f6891da8e739e5831553820b99f1a33fc7fa4f01..eea794fcd94ac3847867a33d5b213f0f957eeeed 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -53,6 +53,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
 
   setOperationAction(ISD::SETCC, MVT::i32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
 
   setSchedulingPreference(SchedulingForRegPressure);
   computeRegisterProperties();
@@ -71,7 +72,9 @@ namespace llvm {
 
       CMP,
 
-      SELECT
+      SELECT,
+
+      BR
     };
   }
 }
@@ -83,6 +86,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
   case ARMISD::SELECT:        return "ARMISD::SELECT";
   case ARMISD::CMP:           return "ARMISD::CMP";
+  case ARMISD::BR:            return "ARMISD::BR";
   }
 }
 
@@ -312,6 +316,19 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
   return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp);
 }
 
+static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
+  SDOperand  Chain = Op.getOperand(0);
+  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
+  SDOperand    LHS = Op.getOperand(2);
+  SDOperand    RHS = Op.getOperand(3);
+  SDOperand   Dest = Op.getOperand(4);
+
+  assert(CC == ISD::SETNE);
+
+  SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
+  return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, Cmp);
+}
+
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default:
@@ -329,6 +346,8 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     return LowerRET(Op, DAG);
   case ISD::SELECT_CC:
     return LowerSELECT_CC(Op, DAG);
+  case ISD::BR_CC:
+    return LowerBR_CC(Op, DAG);
   }
 }
 

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 87e368594d14f803f0aa3b24696b59b217a7332d..a28ec77031bdb611bc48612816c2190b0e4a68ce 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -37,6 +37,8 @@ class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
   let Pattern = pattern;
 }
 
+def brtarget : Operand<OtherVT>;
+
 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
 def callseq_start  : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
                             [SDNPHasChain, SDNPOutFlag]>;
@@ -50,6 +52,9 @@ def retflag        : SDNode<"ARMISD::RET_FLAG", SDTRet,
                           [SDNPHasChain, SDNPOptInFlag]>;
 def armselect      : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
 
+def SDTarmbr       : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
+def armbr          : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
+
 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 def armcmp       : SDNode<"ARMISD::CMP",  SDTVoidBinOp, [SDNPOutFlag]>;
 
@@ -107,6 +112,10 @@ let isTwoAddress = 1 in {
                         [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
 }
 
+def bne    : InstARM<(ops brtarget:$dst),
+                    "bne $dst",
+                    [(armbr bb:$dst)]>;
+
 def cmp      : InstARM<(ops IntRegs:$a, IntRegs:$b),
                       "cmp $a, $b",
                       [(armcmp IntRegs:$a, IntRegs:$b)]>;

diff --git a/test/CodeGen/ARM/branch.ll b/test/CodeGen/ARM/branch.ll
new file mode 100644 (file)
index 0000000..21e4312
--- /dev/null
+++ b/test/CodeGen/ARM/branch.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -march=arm
+void %f(int %a, int* %v) {
+entry:
+       %tmp = seteq int %a, 0          ; <bool> [#uses=1]
+       br bool %tmp, label %cond_true, label %return
+
+cond_true:             ; preds = %entry
+       store int 0, int* %v
+       ret void
+
+return:                ; preds = %entry
+       ret void
+}