Change RET node to include signness information of the return values. i.e.

RET chain, value1, sign1, value2, sign2, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 54c7101e408b1d175d464602e8792a522f829fb0..8312d14dca7fc55e10b9afda5a52082a0cb22294 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -62,8 +62,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
     abort();
   case 1:
     return SDOperand(); // ret void is legal
-  case 2:
-    Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
+  case 3:
+    Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
     break;
   }
 

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 837a911c1971fc4db527225b9b90d66d20f6882c..0073beaa54cabcb80c93ba9d6847420aaaeb2f10 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -231,7 +231,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     Select(Chain, N->getOperand(0));     // Token chain.
     SDOperand InFlag(0,0);
 
-    if (N->getNumOperands() == 2) {
+    if (N->getNumOperands() == 3) {
       SDOperand Val;
       Select(Val, N->getOperand(1));
       if (N->getOperand(1).getValueType() == MVT::i64) {

diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 9de54472de2859c085352ce7cfaa025048a7ab73..6c814589aec452b5b1abc1203060ac0f0588326a 100644 (file)
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -562,7 +562,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
       AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS, 
                                    AR_PFSVal);
       return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
-    case 2: {
+    case 3: {
       // Copy the result into the output register & restore ar.pfs
       MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
       unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index b33aeb8fbb64b9cd29cba2e89478d1c5ef576050..18e1cbacb4c7bb30375174506883d12259ebeb92 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1160,7 +1160,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
     abort();
   case 1: 
     return SDOperand(); // ret void is legal
-  case 2: {
+  case 3: {
     MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
     unsigned ArgReg;
     if (MVT::isVector(ArgVT))
@@ -1180,8 +1180,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
       DAG.getMachineFunction().addLiveOut(ArgReg);
     break;
   }
-  case 3:
-    Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), 
+  case 5:
+    Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3), 
                             SDOperand());
     Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
     // If we haven't noted the R3+R4 are live out, do so now.

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index b5eafaa144a7358ac450782c159f052561ab02c0..ca91dc1a9a03ad7243c32909c9bf5b8d94380c5a 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -857,7 +857,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
       abort();
     case 1: 
       return SDOperand(); // ret void is legal
-    case 2: {
+    case 3: {
       unsigned ArgReg;
       switch(Op.getOperand(1).getValueType()) {
       default: assert(0 && "Unknown type to return!");
@@ -869,8 +869,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
                               SDOperand());
       break;
     }
-    case 3:
-      Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2), 
+    case 5:
+      Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 
                               SDOperand());
       Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
       break;

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1d2f6e4fc8f618b0b6febc54791e189e4fe42731..4aaf991e026e2cb8cd81ebb9d07817a69850e99e 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3326,7 +3326,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
     case 1:    // ret void.
       return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
                         DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
-    case 2: {
+    case 3: {
       MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
       
       if (MVT::isVector(ArgVT)) {
@@ -3394,13 +3394,13 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
       }
       break;
     }
-    case 3:
+    case 5:
       if (DAG.getMachineFunction().liveout_empty()) {
         DAG.getMachineFunction().addLiveOut(X86::EAX);
         DAG.getMachineFunction().addLiveOut(X86::EDX);
       }
 
-      Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2), 
+      Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(3), 
                               SDOperand());
       Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
       break;