The variable SAR's only take one operand too

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22888 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index e78a9df62c881d0728533bb5ee15d3fd539be577..0ebd6299cffaf1dba7f8f49dff7c1c84e576e827 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -3283,7 +3283,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     case MVT::i32: Opc = X86::SAR32rCL; break;
     }
     BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::SETCC: