Put int the getReg cast optimization from x86 so that we generate fewer

move instructions for the register allocator to coalesce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17608 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 1dd946a421f4f90abccbeef8f50d593c6a7d7a46..0e8b7b04c562394cf41307542ab8643e0341125e 100644 (file)
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -502,6 +502,10 @@ unsigned PPC32ISel::getReg(Value *V, MachineBasicBlock *MBB,
     unsigned Reg = makeAnotherReg(V->getType());
     copyConstantToRegister(MBB, IPt, C, Reg);
     return Reg;
+  } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
+    // Do not emit noop casts at all, unless it's a double -> float cast.
+    if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
+      return getReg(CI->getOperand(0), MBB, IPt);
   } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
     unsigned Reg = makeAnotherReg(V->getType());
     unsigned FI = getFixedSizedAllocaFI(AI);
@@ -3129,6 +3133,10 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
   unsigned SrcClass = getClassB(Op->getType());
   unsigned DestClass = getClassB(CI.getType());
 
+  // Noop casts are not emitted: getReg will return the source operand as the
+  // register to use for any uses of the noop cast.
+  if (DestClass == SrcClass) return;
+
   // If this is a cast from a 32-bit integer to a Long type, and the only uses
   // of the cast are GEP instructions, then the cast does not need to be
   // generated explicitly, it will be folded into the GEP.

diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt
index 0e45959ea478674aeae9eae30e63a38af92e2c13..9c7e9e609b82e414712991d4175493f3464da176 100644 (file)
--- a/lib/Target/PowerPC/README.txt
+++ b/lib/Target/PowerPC/README.txt
@@ -1,4 +1,6 @@
 TODO:
+* poor switch statement codegen
+* load/store to alloca'd array or struct.
 * implement not-R0 register GPR class
 * implement scheduling info
 * implement do-loop pass