Next powerpc long double bits. Comparisons work,

although not well, and shortening FP converts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42672 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index d55a4da28e48a500e917c2bbfc28b7a68b2d3a9f..a928968ef90cb28b4d6ed098634b08ec79e86e62 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3314,32 +3314,42 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       MVT::ValueType newVT = Op.getValueType();
       MVT::ValueType oldVT = Op.getOperand(0).getValueType();
       if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
-        // The only way we can lower this is to turn it into a STORE,
-        // LOAD pair, targetting a temporary location (a stack slot).
-
-        // NOTE: there is a choice here between constantly creating new stack
-        // slots and always reusing the same one.  We currently always create
-        // new ones, as reuse may inhibit scheduling.
-        MVT::ValueType slotVT = 
-                (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
-        const Type *Ty = MVT::getTypeForValueType(slotVT);
-        uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
-        unsigned Align  = TLI.getTargetData()->getPrefTypeAlignment(Ty);
-        MachineFunction &MF = DAG.getMachineFunction();
-        int SSFI =
-          MF.getFrameInfo()->CreateStackObject(TySize, Align);
-        SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
-        if (Node->getOpcode() == ISD::FP_EXTEND) {
-          Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
-                                     StackSlot, NULL, 0);
-          Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
-                                     Result, StackSlot, NULL, 0, oldVT);
+        if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) {
+          SDOperand Lo, Hi;
+          ExpandOp(Node->getOperand(0), Lo, Hi);
+          if (newVT == MVT::f64)
+            Result = Hi;
+          else
+            Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi);
+          break;
         } else {
-          Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
-                                     StackSlot, NULL, 0, newVT);
-          Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
+          // The only other way we can lower this is to turn it into a STORE,
+          // LOAD pair, targetting a temporary location (a stack slot).
+
+          // NOTE: there is a choice here between constantly creating new stack
+          // slots and always reusing the same one.  We currently always create
+          // new ones, as reuse may inhibit scheduling.
+          MVT::ValueType slotVT = 
+                  (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
+          const Type *Ty = MVT::getTypeForValueType(slotVT);
+          uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
+          unsigned Align  = TLI.getTargetData()->getPrefTypeAlignment(Ty);
+          MachineFunction &MF = DAG.getMachineFunction();
+          int SSFI =
+            MF.getFrameInfo()->CreateStackObject(TySize, Align);
+          SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
+          if (Node->getOpcode() == ISD::FP_EXTEND) {
+            Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
+                                       StackSlot, NULL, 0);
+            Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
+                                       Result, StackSlot, NULL, 0, oldVT);
+          } else {
+            Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
+                                       StackSlot, NULL, 0, newVT);
+            Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
+          }
+          break;
         }
-        break;
       }
     }
     // FALL THROUGH
@@ -3995,7 +4005,7 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
                                                  SDOperand &RHS,
                                                  SDOperand &CC) {
-  SDOperand Tmp1, Tmp2, Result;    
+  SDOperand Tmp1, Tmp2, Tmp3, Result;    
   
   switch (getTypeAction(LHS.getValueType())) {
   case Legal:
@@ -4126,8 +4136,27 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
 
     SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
     ExpandOp(LHS, LHSLo, LHSHi);
-    ExpandOp(RHS, RHSLo, RHSHi);    
-    switch (cast<CondCodeSDNode>(CC)->get()) {
+    ExpandOp(RHS, RHSLo, RHSHi);
+    ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
+
+    if (VT==MVT::ppcf128) {
+      // FIXME:  This generated code sucks.  We want to generate
+      //         FCMP crN, hi1, hi2
+      //         BNE crN, L:
+      //         FCMP crN, lo1, lo2
+      // The following can be improved, but not that much.
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
+      Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
+      Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
+      Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
+      Tmp2 = SDOperand();
+      break;
+    }
+
+    switch (CCCode) {
     case ISD::SETEQ:
     case ISD::SETNE:
       if (RHSLo == RHSHi)
@@ -4159,7 +4188,6 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
 
       // FIXME: This generated code sucks.
       ISD::CondCode LowCC;
-      ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
       switch (CCCode) {
       default: assert(0 && "Unknown integer setcc!");
       case ISD::SETLT:

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index ec1046fcb14d828fae87387093a6e78b27850aa3..ae29095dd8f9983e21aa597577878fa35c6ddaed 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -73,6 +73,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
   setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
   setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
 
+  // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
+  setConvertAction(MVT::ppcf128, MVT::f64, Expand);
+  setConvertAction(MVT::ppcf128, MVT::f32, Expand);
+
   // PowerPC has no intrinsics for these particular operations
   setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
   setOperationAction(ISD::MEMSET, MVT::Other, Expand);