drm/i915/gen9: Implement WaDisableKillLogic for gen 9
authorNick Hoath <nicholas.hoath@intel.com>
Tue, 14 Jul 2015 13:41:15 +0000 (14:41 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 15 Jul 2015 12:29:19 +0000 (14:29 +0200)
v2: Patch leakage fixed

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 97794bc753f27fff13147050718c56347c69b37a..ef5f69a1607f22eddd7c1e51e3af9b3b564d1c29 100644 (file)
 #define GAM_ECOCHK                     0x4090
 #define   BDW_DISABLE_HDC_INVALIDATION (1<<25)
 #define   ECOCHK_SNB_BIT               (1<<10)
+#define   ECOCHK_DIS_TLB               (1<<8)
 #define   HSW_ECOCHK_ARB_PRIO_SOL      (1<<6)
 #define   ECOCHK_PPGTT_CACHE64B                (0x3<<3)
 #define   ECOCHK_PPGTT_CACHE4B         (0x0<<3)
index 025978548fb6b4876379b18ba9c8e5114640f4c8..3a48c4f21f1181144cf3bfa8cec51a381445173e 100644 (file)
@@ -59,6 +59,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
        /* WaEnableLbsSlaRetryTimerDecrement:skl */
        I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
                   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+
+       /* WaDisableKillLogic:bxt,skl */
+       I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+                  ECOCHK_DIS_TLB);
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)