rk3288 gpu : update r4p0_eac : runtime_on clock freq set to 500M
authorCody Xie <Cody.Xie@rock-chips.com>
Wed, 9 Apr 2014 09:21:22 +0000 (17:21 +0800)
committerCody Xie <Cody.Xie@rock-chips.com>
Wed, 9 Apr 2014 09:21:49 +0000 (17:21 +0800)
drivers/gpu/arm/midgard/platform/rk/mali_kbase_config_rk.c

index ac66fd035d2b6e72f0c848730e45743f5f8faa75..237c75fe7c345f081a1d83c0a5d650b4ee7c1aeb 100755 (executable)
@@ -109,7 +109,7 @@ static int mali_pm_notifier(struct notifier_block *nb,unsigned long event,void*
                case PM_SUSPEND_PREPARE:
 #ifdef CONFIG_MALI_MIDGARD_DVFS
                        //if (kbase_platform_dvfs_enable(false, MALI_DVFS_BL_CONFIG_FREQ)!= MALI_TRUE)
-                       if (kbase_platform_dvfs_enable(false, p_mali_dvfs_infotbl[MALI_DVFS_STEP-1].clock)!= MALI_TRUE)
+                       if (kbase_platform_dvfs_enable(false, p_mali_dvfs_infotbl[0].clock)!= MALI_TRUE)
                                err = NOTIFY_BAD;
 #endif
                        break;
@@ -219,7 +219,7 @@ static int pm_callback_runtime_on(kbase_device *kbdev)
 #ifdef CONFIG_MALI_MIDGARD_DVFS
        if (platform->dvfs_enabled) {
                //if (kbase_platform_dvfs_enable(true, MALI_DVFS_START_FREQ)!= MALI_TRUE)
-               if (kbase_platform_dvfs_enable(true, p_mali_dvfs_infotbl[0].clock)!= MALI_TRUE)
+               if (kbase_platform_dvfs_enable(true, p_mali_dvfs_infotbl[MALI_DVFS_STEP-1].clock)!= MALI_TRUE)
                        return -EPERM;
        } else {
                if (kbase_platform_dvfs_enable(false, MALI_DVFS_CURRENT_FREQ)!= MALI_TRUE)