Add support for parsing #-0 on non-memory-operand immediate values, and add a testcas...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index b00416fe4066dcdbc483aea8bf1ec226a72ca5ca..2c7accd61c76e7e89b498449f4b1b3a602e793ce 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -717,7 +717,7 @@ public:
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     if (!CE) return false;
     int64_t Val = CE->getValue();
-    return Val > -256 && Val < 256;
+    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
   }
 
   bool isMSRMask() const { return Kind == MSRMask; }
@@ -1106,6 +1106,7 @@ public:
     assert(CE && "non-constant post-idx-imm8 operand!");
     int Imm = CE->getValue();
     bool isAdd = Imm >= 0;
+    if (Imm == INT32_MIN) Imm = 0;
     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
     Inst.addOperand(MCOperand::CreateImm(Imm));
   }
@@ -2746,17 +2747,27 @@ bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
     return parseMemory(Operands);
   case AsmToken::LCurly:
     return parseRegisterList(Operands);
-  case AsmToken::Hash:
+  case AsmToken::Hash: {
     // #42 -> immediate.
     // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
     S = Parser.getTok().getLoc();
     Parser.Lex();
+    bool isNegative = Parser.getTok().is(AsmToken::Minus);
     const MCExpr *ImmVal;
     if (getParser().ParseExpression(ImmVal))
       return true;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
+    if (!CE) {
+      Error(S, "constant expression expected");
+      return MatchOperand_ParseFail;
+    }
+    int32_t Val = CE->getValue();
+    if (isNegative && Val == 0)
+      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
     Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
     return false;
+  }
   case AsmToken::Colon: {
     // ":lower16:" and ":upper16:" expression prefixes
     // FIXME: Check it's an expression prefix,

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index ffb1f8a20165d5cb1951da2649a53800e6bf30df..d466662bd2cbddd1c591fddae17daa71e5b7c91c 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -687,6 +687,14 @@ Lforward:
 @ CHECK: ldrex r1, [r7]                @ encoding: [0x9f,0x1f,0x97,0xe1]
 @ CHECK: ldrexd        r6, r7, [r8]            @ encoding: [0x9f,0x6f,0xb8,0xe1]
 
+@------------------------------------------------------------------------------
+@ LDRHT
+@------------------------------------------------------------------------------
+        ldrhthi        r8, [r11], #-0
+        ldrhthi        r8, [r11], #0
+
+@ CHECK: ldrhthi       r8, [r11], #-0          @ encoding: [0xb0,0x80,0x7b,0x80]
+@ CHECK: ldrhthi       r8, [r11], #0           @ encoding: [0xb0,0x80,0xfb,0x80]
 
 @------------------------------------------------------------------------------
 @ FIXME: LSL