Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198945 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 84d1476d04427d5c75628cce2cd31ae2b4731bd1..c4303f03003cdecae5500aa3b085ed74f9187c08 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -630,15 +630,19 @@ void ARMAsmPrinter::emitAttributes() {
   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
                     getArchForCPU(CPUString, Subtarget));
 
-  if (Subtarget->isAClass()) {
-    ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
-                      ARMBuildAttrs::ApplicationProfile);
-  } else if (Subtarget->isRClass()) {
-    ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
-                      ARMBuildAttrs::RealTimeProfile);
-  } else if (Subtarget->isMClass()){
-    ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
-                      ARMBuildAttrs::MicroControllerProfile);
+  // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
+  // profile is not applicable (e.g. pre v7, or cross-profile code)". 
+  if (Subtarget->hasV7Ops()) {
+    if (Subtarget->isAClass()) {
+      ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+                        ARMBuildAttrs::ApplicationProfile);
+    } else if (Subtarget->isRClass()) {
+      ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+                        ARMBuildAttrs::RealTimeProfile);
+    } else if (Subtarget->isMClass()) {
+      ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+                        ARMBuildAttrs::MicroControllerProfile);
+    }
   }
 
   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?

diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index fd9151f2d206b65f903a1e94f27af2122d0ee999..ec3c5fe842281746a9e96c05d7ffa7d4c316d115 100644 (file)
--- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -692,7 +692,6 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
     break;
 
   case ARM::ARMV6M:
-    setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
     setAttributeItem(THUMB_ISA_use, Allowed, false);
     break;
 

diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll
index faf89728a84b325e8cfd4a26c9879c732a28a4db..ce7a31f3dc547c3faef33fcd849369a240d4d84e 100644 (file)
--- a/test/CodeGen/ARM/build-attributes.ll
+++ b/test/CodeGen/ARM/build-attributes.ll
@@ -43,7 +43,7 @@
 ; V6-NOT:    .eabi_attribute 68
 
 ; V6M:  .eabi_attribute 6, 12
-; V6M:  .eabi_attribute 7, 77
+; V6M-NOT:  .eabi_attribute 7
 ; V6M:  .eabi_attribute 8, 0
 ; V6M:  .eabi_attribute 9, 1
 ; V6M:  .eabi_attribute 24, 1
@@ -333,7 +333,7 @@
 
 ; CORTEX-M0:  .cpu cortex-m0
 ; CORTEX-M0:  .eabi_attribute 6, 12
-; CORTEX-M0:  .eabi_attribute 7, 77
+; CORTEX-M0-NOT:  .eabi_attribute 7
 ; CORTEX-M0:  .eabi_attribute 8, 0
 ; CORTEX-M0:  .eabi_attribute 9, 1
 ; CORTEX-M0:  .eabi_attribute 24, 1

diff --git a/test/MC/ARM/directive-arch-armv6-m.s b/test/MC/ARM/directive-arch-armv6-m.s
index 5a28905b6a94a8d6e81a0f935932f698e5c3e96c..fc7082790364c85e9a27915ed2106103761792f5 100644 (file)
--- a/test/MC/ARM/directive-arch-armv6-m.s
+++ b/test/MC/ARM/directive-arch-armv6-m.s
@@ -19,12 +19,12 @@
 @ CHECK-OBJ:    ]
 @ CHECK-OBJ:    Address: 0x0
 @ CHECK-OBJ:    Offset: 0x34
-@ CHECK-OBJ:    Size: 27
+@ CHECK-OBJ:    Size: 25
 @ CHECK-OBJ:    Link: 0
 @ CHECK-OBJ:    Info: 0
 @ CHECK-OBJ:    AddressAlignment: 1
 @ CHECK-OBJ:    EntrySize: 0
 @ CHECK-OBJ:    SectionData (
-@ CHECK-OBJ:      0000: 411A0000 00616561 62690001 10000000  |A....aeabi......|
-@ CHECK-OBJ:      0010: 05362D4D 00060B07 4D0901             |.6-M....M..|
+@ CHECK-OBJ:      0000: 41180000 00616561 62690001 0E000000  |A....aeabi......|
+@ CHECK-OBJ:      0010: 05362D4D 00060B09 01                 |.6-M.....|
 @ CHECK-OBJ:    )