drm/nouveau/bus: namespace + nvidia gpu names (no binary change)

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
index 2d40f0c2fdfc6dc9b1a25e7d0f53cf97cdd21d93..fba83c04849eae02fcf410e791836763ca9f4cb0 100644 (file)
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
@@ -1,53 +1,50 @@
-#ifndef __NOUVEAU_BUS_H__
-#define __NOUVEAU_BUS_H__
-
+#ifndef __NVKM_BUS_H__
+#define __NVKM_BUS_H__
 #include <core/subdev.h>
-#include <core/device.h>
 
-struct nouveau_bus_intr {
+struct nvkm_bus_intr {
        u32 stat;
        u32 unit;
 };
 
-struct nouveau_bus {
-       struct nouveau_subdev base;
-       int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
+struct nvkm_bus {
+       struct nvkm_subdev base;
+       int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
        u32 hwsq_size;
 };
 
-static inline struct nouveau_bus *
-nouveau_bus(void *obj)
+static inline struct nvkm_bus *
+nvkm_bus(void *obj)
 {
-       return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_BUS);
+       return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS);
 }
 
-#define nouveau_bus_create(p, e, o, d)                                         \
-       nouveau_subdev_create_((p), (e), (o), 0, "PBUS", "master",             \
+#define nvkm_bus_create(p, e, o, d)                                         \
+       nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master",             \
                               sizeof(**d), (void **)d)
-#define nouveau_bus_destroy(p)                                                 \
-       nouveau_subdev_destroy(&(p)->base)
-#define nouveau_bus_init(p)                                                    \
-       nouveau_subdev_init(&(p)->base)
-#define nouveau_bus_fini(p, s)                                                 \
-       nouveau_subdev_fini(&(p)->base, (s))
-
-#define _nouveau_bus_dtor _nouveau_subdev_dtor
-#define _nouveau_bus_init _nouveau_subdev_init
-#define _nouveau_bus_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass *nv04_bus_oclass;
-extern struct nouveau_oclass *nv31_bus_oclass;
-extern struct nouveau_oclass *nv50_bus_oclass;
-extern struct nouveau_oclass *nv94_bus_oclass;
-extern struct nouveau_oclass *nvc0_bus_oclass;
+#define nvkm_bus_destroy(p)                                                 \
+       nvkm_subdev_destroy(&(p)->base)
+#define nvkm_bus_init(p)                                                    \
+       nvkm_subdev_init(&(p)->base)
+#define nvkm_bus_fini(p, s)                                                 \
+       nvkm_subdev_fini(&(p)->base, (s))
+
+#define _nvkm_bus_dtor _nvkm_subdev_dtor
+#define _nvkm_bus_init _nvkm_subdev_init
+#define _nvkm_bus_fini _nvkm_subdev_fini
+
+extern struct nvkm_oclass *nv04_bus_oclass;
+extern struct nvkm_oclass *nv31_bus_oclass;
+extern struct nvkm_oclass *nv50_bus_oclass;
+extern struct nvkm_oclass *g94_bus_oclass;
+extern struct nvkm_oclass *gf100_bus_oclass;
 
 /* interface to sequencer */
-struct nouveau_hwsq;
-int  nouveau_hwsq_init(struct nouveau_bus *, struct nouveau_hwsq **);
-int  nouveau_hwsq_fini(struct nouveau_hwsq **, bool exec);
-void nouveau_hwsq_wr32(struct nouveau_hwsq *, u32 addr, u32 data);
-void nouveau_hwsq_setf(struct nouveau_hwsq *, u8 flag, int data);
-void nouveau_hwsq_wait(struct nouveau_hwsq *, u8 flag, u8 data);
-void nouveau_hwsq_nsec(struct nouveau_hwsq *, u32 nsec);
-
+struct nvkm_hwsq;
+int  nvkm_hwsq_init(struct nvkm_bus *, struct nvkm_hwsq **);
+int  nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec);
+void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data);
+void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data);
+void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data);
+void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec);
 #endif

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 29dbe1693480d1d9396788ad56e6ef9d3a23b512..f6004cc543c0970b2afa42cf61cff9466b96bef8 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -70,7 +70,7 @@ gm100_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm107_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
@@ -114,7 +114,7 @@ gm100_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm204_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 4f100b261f286b8b1bfbce4a5119e4bac66b2ebc..e60deaee4d2f587943961f6f4a4fc61057f3f2f5 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -185,7 +185,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -214,7 +214,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -243,7 +243,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -272,7 +272,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -301,7 +301,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -330,7 +330,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -359,7 +359,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -390,7 +390,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -420,7 +420,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
@@ -450,7 +450,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvaf_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvaf_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 5e4608fba660548d8856b1d1818238ca428af536..89ff7d0d630bc73fb0140e4cd93b680cfdc99f6f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -70,7 +70,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -103,7 +103,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -136,7 +136,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -168,7 +168,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -201,7 +201,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -233,7 +233,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -265,7 +265,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -298,7 +298,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;
@@ -330,7 +330,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index a488b30304cf2a00d3c6068a907dec8f3b405263..11805f72f4e9de640f1d4e6f2baa435cfc49ff75 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -70,7 +70,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
@@ -104,7 +104,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
@@ -138,7 +138,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
@@ -165,7 +165,7 @@ nve0_identify(struct nouveau_device *device)
                device->cname = "GK20A";
                device->oclass[NVDEV_SUBDEV_CLK    ] = &gk20a_clk_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  gk20a_fb_oclass;
@@ -194,7 +194,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
@@ -228,7 +228,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
@@ -262,7 +262,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
@@ -295,7 +295,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
                device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+               device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
                device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
index 633e9b4b6a3aeee81d3f5e13c311e5333bccb1da..83d80b13f14964fc44589bc9451ddba554d072e5 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
@@ -2,5 +2,5 @@ nvkm-y += nvkm/subdev/bus/hwsq.o
 nvkm-y += nvkm/subdev/bus/nv04.o
 nvkm-y += nvkm/subdev/bus/nv31.o
 nvkm-y += nvkm/subdev/bus/nv50.o
-nvkm-y += nvkm/subdev/bus/nv94.o
-nvkm-y += nvkm/subdev/bus/nvc0.o
+nvkm-y += nvkm/subdev/bus/g94.o
+nvkm-y += nvkm/subdev/bus/gf100.o

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
new file mode 100644 (file)
index 0000000..cbe699e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2012 Nouveau Community
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres <martin.peres@labri.fr>
+ *          Ben Skeggs
+ */
+#include "nv04.h"
+
+#include <subdev/timer.h>
+
+static int
+g94_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
+{
+       struct nv50_bus_priv *priv = (void *)pbus;
+       int i;
+
+       nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
+       nv_wr32(pbus, 0x001304, 0x00000000);
+       nv_wr32(pbus, 0x001318, 0x00000000);
+       for (i = 0; i < size; i++)
+               nv_wr32(priv, 0x080000 + (i * 4), data[i]);
+       nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
+       nv_wr32(pbus, 0x00130c, 0x00000001);
+
+       return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
+}
+
+struct nvkm_oclass *
+g94_bus_oclass = &(struct nv04_bus_impl) {
+       .base.handle = NV_SUBDEV(BUS, 0x94),
+       .base.ofuncs = &(struct nvkm_ofuncs) {
+               .ctor = nv04_bus_ctor,
+               .dtor = _nvkm_bus_dtor,
+               .init = nv50_bus_init,
+               .fini = _nvkm_bus_fini,
+       },
+       .intr = nv50_bus_intr,
+       .hwsq_exec = g94_bus_hwsq_exec,
+       .hwsq_size = 128,
+}.base;

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
new file mode 100644 (file)
index 0000000..ebc63ba
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2012 Nouveau Community
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres <martin.peres@labri.fr>
+ *          Ben Skeggs
+ */
+#include "nv04.h"
+
+static void
+gf100_bus_intr(struct nvkm_subdev *subdev)
+{
+       struct nvkm_bus *pbus = nvkm_bus(subdev);
+       u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
+
+       if (stat & 0x0000000e) {
+               u32 addr = nv_rd32(pbus, 0x009084);
+               u32 data = nv_rd32(pbus, 0x009088);
+
+               nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
+                        (addr & 0x00000002) ? "write" : "read", data,
+                        (addr & 0x00fffffc),
+                        (stat & 0x00000002) ? "!ENGINE " : "",
+                        (stat & 0x00000004) ? "IBUS " : "",
+                        (stat & 0x00000008) ? "TIMEOUT " : "");
+
+               nv_wr32(pbus, 0x009084, 0x00000000);
+               nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
+               stat &= ~0x0000000e;
+       }
+
+       if (stat) {
+               nv_error(pbus, "unknown intr 0x%08x\n", stat);
+               nv_mask(pbus, 0x001140, stat, 0x00000000);
+       }
+}
+
+static int
+gf100_bus_init(struct nvkm_object *object)
+{
+       struct nv04_bus_priv *priv = (void *)object;
+       int ret;
+
+       ret = nvkm_bus_init(&priv->base);
+       if (ret)
+               return ret;
+
+       nv_wr32(priv, 0x001100, 0xffffffff);
+       nv_wr32(priv, 0x001140, 0x0000000e);
+       return 0;
+}
+
+struct nvkm_oclass *
+gf100_bus_oclass = &(struct nv04_bus_impl) {
+       .base.handle = NV_SUBDEV(BUS, 0xc0),
+       .base.ofuncs = &(struct nvkm_ofuncs) {
+               .ctor = nv04_bus_ctor,
+               .dtor = _nvkm_bus_dtor,
+               .init = gf100_bus_init,
+               .fini = _nvkm_bus_fini,
+       },
+       .intr = gf100_bus_intr,
+}.base;

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
index f757470e228461c559538ab36a7fd12eb48f9271..b8853bf16b23ed9e9287f02e29e1c70ddb2e81c6 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
@@ -21,12 +21,10 @@
  *
  * Authors: Ben Skeggs <bskeggs@redhat.com>
  */
-
-#include <subdev/timer.h>
 #include <subdev/bus.h>
 
-struct nouveau_hwsq {
-       struct nouveau_bus *pbus;
+struct nvkm_hwsq {
+       struct nvkm_bus *pbus;
        u32 addr;
        u32 data;
        struct {
@@ -36,16 +34,16 @@ struct nouveau_hwsq {
 };
 
 static void
-hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[])
+hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[])
 {
        memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
        hwsq->c.size += size;
 }
 
 int
-nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq)
+nvkm_hwsq_init(struct nvkm_bus *pbus, struct nvkm_hwsq **phwsq)
 {
-       struct nouveau_hwsq *hwsq;
+       struct nvkm_hwsq *hwsq;
 
        hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
        if (hwsq) {
@@ -60,12 +58,12 @@ nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq)
 }
 
 int
-nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
+nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
 {
-       struct nouveau_hwsq *hwsq = *phwsq;
+       struct nvkm_hwsq *hwsq = *phwsq;
        int ret = 0, i;
        if (hwsq) {
-               struct nouveau_bus *pbus = hwsq->pbus;
+               struct nvkm_bus *pbus = hwsq->pbus;
                hwsq->c.size = (hwsq->c.size + 4) / 4;
                if (hwsq->c.size <= pbus->hwsq_size) {
                        if (exec)
@@ -88,7 +86,7 @@ nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
 }
 
 void
-nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
+nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
 {
        nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data);
 
@@ -113,7 +111,7 @@ nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
 }
 
 void
-nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
+nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
 {
        nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data);
        flag += 0x80;
@@ -125,14 +123,14 @@ nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
 }
 
 void
-nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data)
+nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)
 {
        nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data);
        hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
 }
 
 void
-nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec)
+nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec)
 {
        u8 shift = 0, usec = nsec / 1000;
        while (usec & ~3) {

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
index 12176f9c1bc635299fd6ca3ed1df2ad90de7d370..3394a5ea8a9fb62719b630b55162a48dda22b34d 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
@@ -1,11 +1,10 @@
 #ifndef __NVKM_BUS_HWSQ_H__
 #define __NVKM_BUS_HWSQ_H__
-
 #include <subdev/bus.h>
 
 struct hwsq {
-       struct nouveau_subdev *subdev;
-       struct nouveau_hwsq *hwsq;
+       struct nvkm_subdev *subdev;
+       struct nvkm_hwsq *hwsq;
        int sequence;
 };
 
@@ -34,12 +33,12 @@ hwsq_reg(u32 addr)
 }
 
 static inline int
-hwsq_init(struct hwsq *ram, struct nouveau_subdev *subdev)
+hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
 {
-       struct nouveau_bus *pbus = nouveau_bus(subdev);
+       struct nvkm_bus *pbus = nvkm_bus(subdev);
        int ret;
 
-       ret = nouveau_hwsq_init(pbus, &ram->hwsq);
+       ret = nvkm_hwsq_init(pbus, &ram->hwsq);
        if (ret)
                return ret;
 
@@ -53,7 +52,7 @@ hwsq_exec(struct hwsq *ram, bool exec)
 {
        int ret = 0;
        if (ram->subdev) {
-               ret = nouveau_hwsq_fini(&ram->hwsq, exec);
+               ret = nvkm_hwsq_fini(&ram->hwsq, exec);
                ram->subdev = NULL;
        }
        return ret;
@@ -73,8 +72,8 @@ hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
        reg->sequence = ram->sequence;
        reg->data = data;
        if (reg->addr[0] != reg->addr[1])
-               nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
-       nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
+               nvkm_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
+       nvkm_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
 }
 
 static inline void
@@ -95,19 +94,18 @@ hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
 static inline void
 hwsq_setf(struct hwsq *ram, u8 flag, int data)
 {
-       nouveau_hwsq_setf(ram->hwsq, flag, data);
+       nvkm_hwsq_setf(ram->hwsq, flag, data);
 }
 
 static inline void
 hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
 {
-       nouveau_hwsq_wait(ram->hwsq, flag, data);
+       nvkm_hwsq_wait(ram->hwsq, flag, data);
 }
 
 static inline void
 hwsq_nsec(struct hwsq *ram, u32 nsec)
 {
-       nouveau_hwsq_nsec(ram->hwsq, nsec);
+       nvkm_hwsq_nsec(ram->hwsq, nsec);
 }
-
 #endif

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
index 23921b5351dba6639f02b7dafaa552946b72b13a..19c8e50eeff7fbff6412993efc8e43e1574b961b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
@@ -22,13 +22,12 @@
  * Authors: Martin Peres <martin.peres@labri.fr>
  *          Ben Skeggs
  */
-
 #include "nv04.h"
 
 static void
-nv04_bus_intr(struct nouveau_subdev *subdev)
+nv04_bus_intr(struct nvkm_subdev *subdev)
 {
-       struct nouveau_bus *pbus = nouveau_bus(subdev);
+       struct nvkm_bus *pbus = nvkm_bus(subdev);
        u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
 
        if (stat & 0x00000001) {
@@ -38,7 +37,7 @@ nv04_bus_intr(struct nouveau_subdev *subdev)
        }
 
        if (stat & 0x00000110) {
-               subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO);
+               subdev = nvkm_subdev(subdev, NVDEV_SUBDEV_GPIO);
                if (subdev && subdev->intr)
                        subdev->intr(subdev);
                stat &= ~0x00000110;
@@ -52,26 +51,26 @@ nv04_bus_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv04_bus_init(struct nouveau_object *object)
+nv04_bus_init(struct nvkm_object *object)
 {
        struct nv04_bus_priv *priv = (void *)object;
 
        nv_wr32(priv, 0x001100, 0xffffffff);
        nv_wr32(priv, 0x001140, 0x00000111);
 
-       return nouveau_bus_init(&priv->base);
+       return nvkm_bus_init(&priv->base);
 }
 
 int
-nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-             struct nouveau_oclass *oclass, void *data, u32 size,
-             struct nouveau_object **pobject)
+nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+             struct nvkm_oclass *oclass, void *data, u32 size,
+             struct nvkm_object **pobject)
 {
        struct nv04_bus_impl *impl = (void *)oclass;
        struct nv04_bus_priv *priv;
        int ret;
 
-       ret = nouveau_bus_create(parent, engine, oclass, &priv);
+       ret = nvkm_bus_create(parent, engine, oclass, &priv);
        *pobject = nv_object(priv);
        if (ret)
                return ret;
@@ -82,14 +81,14 @@ nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nv04_bus_oclass = &(struct nv04_bus_impl) {
        .base.handle = NV_SUBDEV(BUS, 0x04),
-       .base.ofuncs = &(struct nouveau_ofuncs) {
+       .base.ofuncs = &(struct nvkm_ofuncs) {
                .ctor = nv04_bus_ctor,
-               .dtor = _nouveau_bus_dtor,
+               .dtor = _nvkm_bus_dtor,
                .init = nv04_bus_init,
-               .fini = _nouveau_bus_fini,
+               .fini = _nvkm_bus_fini,
        },
        .intr = nv04_bus_intr,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
index 4d7602450a20e5140fe199c9a0ec23dd94f1a25a..3ddc8f91b1e37a024f479ddef1b0edf3d1d097b3 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
@@ -1,23 +1,21 @@
 #ifndef __NVKM_BUS_NV04_H__
 #define __NVKM_BUS_NV04_H__
-
 #include <subdev/bus.h>
 
 struct nv04_bus_priv {
-       struct nouveau_bus base;
+       struct nvkm_bus base;
 };
 
-int  nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *,
-                  struct nouveau_oclass *, void *, u32,
-                  struct nouveau_object **);
-int  nv50_bus_init(struct nouveau_object *);
-void nv50_bus_intr(struct nouveau_subdev *);
+int  nv04_bus_ctor(struct nvkm_object *, struct nvkm_object *,
+                  struct nvkm_oclass *, void *, u32,
+                  struct nvkm_object **);
+int  nv50_bus_init(struct nvkm_object *);
+void nv50_bus_intr(struct nvkm_subdev *);
 
 struct nv04_bus_impl {
-       struct nouveau_oclass base;
-       void (*intr)(struct nouveau_subdev *);
-       int  (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
+       struct nvkm_oclass base;
+       void (*intr)(struct nvkm_subdev *);
+       int  (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
        u32  hwsq_size;
 };
-
 #endif

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
index 94da46f61627d044ef4a9ae61c940c8ca687c22c..c5739bce805240c97d82c969fd86c91c20cae0fd 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
@@ -22,18 +22,17 @@
  * Authors: Martin Peres <martin.peres@labri.fr>
  *          Ben Skeggs
  */
-
 #include "nv04.h"
 
 static void
-nv31_bus_intr(struct nouveau_subdev *subdev)
+nv31_bus_intr(struct nvkm_subdev *subdev)
 {
-       struct nouveau_bus *pbus = nouveau_bus(subdev);
+       struct nvkm_bus *pbus = nvkm_bus(subdev);
        u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
        u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);
 
        if (gpio) {
-               subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO);
+               subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_GPIO);
                if (subdev && subdev->intr)
                        subdev->intr(subdev);
        }
@@ -51,7 +50,7 @@ nv31_bus_intr(struct nouveau_subdev *subdev)
        }
 
        if (stat & 0x00070000) {
-               subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
+               subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
                if (subdev && subdev->intr)
                        subdev->intr(subdev);
                stat &= ~0x00070000;
@@ -65,12 +64,12 @@ nv31_bus_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv31_bus_init(struct nouveau_object *object)
+nv31_bus_init(struct nvkm_object *object)
 {
        struct nv04_bus_priv *priv = (void *)object;
        int ret;
 
-       ret = nouveau_bus_init(&priv->base);
+       ret = nvkm_bus_init(&priv->base);
        if (ret)
                return ret;
 
@@ -79,14 +78,14 @@ nv31_bus_init(struct nouveau_object *object)
        return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nv31_bus_oclass = &(struct nv04_bus_impl) {
        .base.handle = NV_SUBDEV(BUS, 0x31),
-       .base.ofuncs = &(struct nouveau_ofuncs) {
+       .base.ofuncs = &(struct nvkm_ofuncs) {
                .ctor = nv04_bus_ctor,
-               .dtor = _nouveau_bus_dtor,
+               .dtor = _nvkm_bus_dtor,
                .init = nv31_bus_init,
-               .fini = _nouveau_bus_fini,
+               .fini = _nvkm_bus_fini,
        },
        .intr = nv31_bus_intr,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
index 11918f7e2aca1cffbd01af23263ca136014ea5d3..1987863d71eed632f394d8c60e56952d839dcd16 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
@@ -22,13 +22,12 @@
  * Authors: Martin Peres <martin.peres@labri.fr>
  *          Ben Skeggs
  */
+#include "nv04.h"
 
 #include <subdev/timer.h>
 
-#include "nv04.h"
-
 static int
-nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
+nv50_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
 {
        struct nv50_bus_priv *priv = (void *)pbus;
        int i;
@@ -44,9 +43,9 @@ nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
 }
 
 void
-nv50_bus_intr(struct nouveau_subdev *subdev)
+nv50_bus_intr(struct nvkm_subdev *subdev)
 {
-       struct nouveau_bus *pbus = nouveau_bus(subdev);
+       struct nvkm_bus *pbus = nvkm_bus(subdev);
        u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
 
        if (stat & 0x00000008) {
@@ -62,7 +61,7 @@ nv50_bus_intr(struct nouveau_subdev *subdev)
        }
 
        if (stat & 0x00010000) {
-               subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
+               subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
                if (subdev && subdev->intr)
                        subdev->intr(subdev);
                stat &= ~0x00010000;
@@ -76,12 +75,12 @@ nv50_bus_intr(struct nouveau_subdev *subdev)
 }
 
 int
-nv50_bus_init(struct nouveau_object *object)
+nv50_bus_init(struct nvkm_object *object)
 {
        struct nv04_bus_priv *priv = (void *)object;
        int ret;
 
-       ret = nouveau_bus_init(&priv->base);
+       ret = nvkm_bus_init(&priv->base);
        if (ret)
                return ret;
 
@@ -90,14 +89,14 @@ nv50_bus_init(struct nouveau_object *object)
        return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nv50_bus_oclass = &(struct nv04_bus_impl) {
        .base.handle = NV_SUBDEV(BUS, 0x50),
-       .base.ofuncs = &(struct nouveau_ofuncs) {
+       .base.ofuncs = &(struct nvkm_ofuncs) {
                .ctor = nv04_bus_ctor,
-               .dtor = _nouveau_bus_dtor,
+               .dtor = _nvkm_bus_dtor,
                .init = nv50_bus_init,
-               .fini = _nouveau_bus_fini,
+               .fini = _nvkm_bus_fini,
        },
        .intr = nv50_bus_intr,
        .hwsq_exec = nv50_bus_hwsq_exec,

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c
deleted file mode 100644 (file)
index d365905..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres <martin.peres@labri.fr>
- *          Ben Skeggs
- */
-
-#include <subdev/timer.h>
-
-#include "nv04.h"
-
-static int
-nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
-{
-       struct nv50_bus_priv *priv = (void *)pbus;
-       int i;
-
-       nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
-       nv_wr32(pbus, 0x001304, 0x00000000);
-       nv_wr32(pbus, 0x001318, 0x00000000);
-       for (i = 0; i < size; i++)
-               nv_wr32(priv, 0x080000 + (i * 4), data[i]);
-       nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
-       nv_wr32(pbus, 0x00130c, 0x00000001);
-
-       return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
-}
-
-struct nouveau_oclass *
-nv94_bus_oclass = &(struct nv04_bus_impl) {
-       .base.handle = NV_SUBDEV(BUS, 0x94),
-       .base.ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = nv04_bus_ctor,
-               .dtor = _nouveau_bus_dtor,
-               .init = nv50_bus_init,
-               .fini = _nouveau_bus_fini,
-       },
-       .intr = nv50_bus_intr,
-       .hwsq_exec = nv94_bus_hwsq_exec,
-       .hwsq_size = 128,
-}.base;

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c
deleted file mode 100644 (file)
index 73839d7..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2012 Nouveau Community
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Martin Peres <martin.peres@labri.fr>
- *          Ben Skeggs
- */
-
-#include "nv04.h"
-
-static void
-nvc0_bus_intr(struct nouveau_subdev *subdev)
-{
-       struct nouveau_bus *pbus = nouveau_bus(subdev);
-       u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
-
-       if (stat & 0x0000000e) {
-               u32 addr = nv_rd32(pbus, 0x009084);
-               u32 data = nv_rd32(pbus, 0x009088);
-
-               nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
-                        (addr & 0x00000002) ? "write" : "read", data,
-                        (addr & 0x00fffffc),
-                        (stat & 0x00000002) ? "!ENGINE " : "",
-                        (stat & 0x00000004) ? "IBUS " : "",
-                        (stat & 0x00000008) ? "TIMEOUT " : "");
-
-               nv_wr32(pbus, 0x009084, 0x00000000);
-               nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
-               stat &= ~0x0000000e;
-       }
-
-       if (stat) {
-               nv_error(pbus, "unknown intr 0x%08x\n", stat);
-               nv_mask(pbus, 0x001140, stat, 0x00000000);
-       }
-}
-
-static int
-nvc0_bus_init(struct nouveau_object *object)
-{
-       struct nv04_bus_priv *priv = (void *)object;
-       int ret;
-
-       ret = nouveau_bus_init(&priv->base);
-       if (ret)
-               return ret;
-
-       nv_wr32(priv, 0x001100, 0xffffffff);
-       nv_wr32(priv, 0x001140, 0x0000000e);
-       return 0;
-}
-
-struct nouveau_oclass *
-nvc0_bus_oclass = &(struct nv04_bus_impl) {
-       .base.handle = NV_SUBDEV(BUS, 0xc0),
-       .base.ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = nv04_bus_ctor,
-               .dtor = _nouveau_bus_dtor,
-               .init = nvc0_bus_init,
-               .fini = _nouveau_bus_fini,
-       },
-       .intr = nvc0_bus_intr,
-}.base;