[TG3]: Increase the PCI MRRS
authorMatt Carlson <mcarlson@broadcom.com>
Tue, 13 Nov 2007 05:19:37 +0000 (21:19 -0800)
committerDavid S. Miller <davem@davemloft.net>
Tue, 13 Nov 2007 05:19:37 +0000 (21:19 -0800)
Previous devices hardcoded the PCI Maximum Read Request Size to 4K.  To
better comply with the PCI spec, the hardware now defaults the MRRS to
512 bytes.  This will yield poor driver performance if left untouched.
This patch increases the MRRS to 4K on driver initialization.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/tg3.c

index ecd64a224e95219d926cc57f6fe923ee0539e16b..72db78b1ec3b4f8fc15f07ae2998a84f65273549 100644 (file)
@@ -5098,12 +5098,15 @@ static void tg3_restore_pci_state(struct tg3 *tp)
 
        pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
+       if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
+               pcie_set_readrq(tp->pdev, 4096);
+       else {
                pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
                                      tp->pci_cacheline_sz);
                pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
                                      tp->pci_lat_timer);
        }
+
        /* Make sure PCI-X relaxed ordering bit is clear. */
        if (tp->pcix_cap) {
                u16 pcix_cmd;
@@ -11215,6 +11218,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
        if (pcie_cap != 0) {
                tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
+
+               pcie_set_readrq(tp->pdev, 4096);
+
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                        u16 lnkctl;