misched: Added ScheduleDAGInstrs::IsPostRA

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index ea0153ecf96243f2d2c4a22e59f97f599882b5d0..e6ca0e847a3b4b42410fb833641ff6734e1c9d55 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -157,7 +157,7 @@ class MachineScheduler : public ScheduleDAGInstrs {
   MachineSchedulerPass *Pass;
 public:
   MachineScheduler(MachineSchedulerPass *P):
-    ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT), Pass(P) {}
+    ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
 
   /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
   /// time to do some work.
@@ -252,7 +252,7 @@ class InstructionShuffler : public ScheduleDAGInstrs {
   MachineSchedulerPass *Pass;
 public:
   InstructionShuffler(MachineSchedulerPass *P):
-    ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT), Pass(P) {}
+    ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
 
   /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
   /// time to do some work.

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index fa832c867a5731d32abf1999055e6e7791d824c7..1e06ee91990f5312bff2be2b8526f132bfb840a1 100644 (file)
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -185,7 +185,7 @@ SchedulePostRATDList::SchedulePostRATDList(
   AliasAnalysis *AA, const RegisterClassInfo &RCI,
   TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
   SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs)
-  : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits), AA(AA),
+  : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
     KillIndices(TRI->getNumRegs())
 {
   const TargetMachine &TM = MF.getTarget();

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index a6556a51c83c55f7544d70d95f42647ae8a4106f..c9255b04dadc3c4ce47b7d8d5fe2b09079d49bd6 100644 (file)
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -33,9 +33,10 @@ using namespace llvm;
 
 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
                                      const MachineLoopInfo &mli,
-                                     const MachineDominatorTree &mdt)
+                                     const MachineDominatorTree &mdt,
+                                     bool IsPostRAFlag)
   : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
-    InstrItins(mf.getTarget().getInstrItineraryData()),
+    InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
     Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
     LoopRegs(MLI, MDT), FirstDbgValue(0) {
   DbgValues.clear();
@@ -253,7 +254,8 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
       unsigned Reg = MO.getReg();
       if (Reg == 0) continue;
 
-      assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
+      assert(!IsPostRA || TRI->isPhysicalRegister(Reg) &&
+             "Virtual register encountered!");
 
       // Optionally add output and anti dependencies. For anti
       // dependencies we use a latency of 0 because for a multi-issue

diff --git a/lib/CodeGen/ScheduleDAGInstrs.h b/lib/CodeGen/ScheduleDAGInstrs.h
index a6233d34821ab870420e9da51adae6d3a3646f1d..f3932892563677889a153d04aff29bb9389ca7ab 100644 (file)
--- a/lib/CodeGen/ScheduleDAGInstrs.h
+++ b/lib/CodeGen/ScheduleDAGInstrs.h
@@ -104,10 +104,13 @@ namespace llvm {
     const MachineFrameInfo *MFI;
     const InstrItineraryData *InstrItins;
 
-    /// Defs, Uses - Remember where defs and uses of each physical register
-    /// are as we iterate upward through the instructions. This is allocated
-    /// here instead of inside BuildSchedGraph to avoid the need for it to be
-    /// initialized and destructed for each block.
+    /// isPostRA flag indicates vregs cannot be present.
+    bool IsPostRA;
+
+    /// Defs, Uses - Remember where defs and uses of each register are as we
+    /// iterate upward through the instructions. This is allocated here instead
+    /// of inside BuildSchedGraph to avoid the need for it to be initialized and
+    /// destructed for each block.
     std::vector<std::vector<SUnit *> > Defs;
     std::vector<std::vector<SUnit *> > Uses;
 
@@ -136,7 +139,8 @@ namespace llvm {
 
     explicit ScheduleDAGInstrs(MachineFunction &mf,
                                const MachineLoopInfo &mli,
-                               const MachineDominatorTree &mdt);
+                               const MachineDominatorTree &mdt,
+                               bool IsPostRAFlag);
 
     virtual ~ScheduleDAGInstrs() {}