The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.

Remove the offending logic and update the test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index fcfe1de17a4ee4aea9e7f0bc3b7ffd3de8ddbd03..da4faf4971a31d21202cded8af92c47f02049aa9 100644 (file)
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -962,11 +962,7 @@ static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn,
 
   unsigned Imm11 = getT1Imm11(insn);
 
-  // When executing a Thumb instruction, PC reads as the address of the current
-  // instruction plus 4.  The assembler subtracts 4 from the difference between
-  // the branch instruction and the target address, disassembler has to add 4 to
-  // to compensate.
-  MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1) + 4));
+  MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1)));
 
   NumOpsAdded = 1;
 
@@ -1747,11 +1743,7 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
     Offset = decodeImm32_BLX(insn);
     break;
   }
-  // When executing a Thumb instruction, PC reads as the address of the current
-  // instruction plus 4.  The assembler subtracts 4 from the difference between
-  // the branch instruction and the target address, disassembler has to add 4 to
-  // to compensate.
-  MI.addOperand(MCOperand::CreateImm(Offset + 4));
+  MI.addOperand(MCOperand::CreateImm(Offset));
 
   // This is an increment as some predicate operands may have been added first.
   NumOpsAdded += 1;

diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index 26a6af8404a3c778085eb447e29d34afaffc29a8..9036b56b2d75d457e65e6349e2012b0db4165bef 100644 (file)
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -6,10 +6,10 @@
 # CHECK:       adcs    r0, r0, #1
 0x50 0xf1 0x01 0x00
 
-# CHECK:       b       #34
+# CHECK:       b       #30
 0x0f 0xe0
 
-# CHECK:       b.w     #-12
+# CHECK:       b.w     #-16
 0xff 0xf7 0xf8 0xaf
 
 # CHECK:       bfi     r2, r10, #0, #1
@@ -128,5 +128,5 @@
 # CHECK: msr cpsr_fc, r0
 0x80 0xf3 0x00 0x89
 
-# CHECK: blx   #0
+# CHECK: blx   #-4
 0xff 0xf7 0xfe 0xef