cell really does support cross-regclass moves, because R3 is in lots of different...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48119 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 5eb467eaf25a2fa8d0573822ad52fc5d30566aaf..bf94cdc0946e4bdfffe8f66ea9abf8a63498550f 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -186,10 +186,15 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const
 {
-  if (DestRC != SrcRC) {
-    cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
-    abort();
-  }
+  // We support cross register class moves for our aliases, such as R3 in any
+  // reg class to any other reg class containing R3.  This is required because
+  // we instruction select bitconvert i64 -> f64 as a noop for example, so our
+  // types have no specific meaning.
+  
+  //if (DestRC != SrcRC) {
+  //  cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
+  //  abort();
+  //}
 
   if (DestRC == SPU::R8CRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);