Handle AssertSext/AssertZext nodes, fixing the regressions last night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23170 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 50b10e41f14a7b29a855699ddd319b4528a07ec1..b1c4a8b324df1a892132c15441f9577b87e3aff1 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -781,6 +781,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     Reg = Result = (N.getValueType() != MVT::Other) ?
                             MakeReg(N.getValueType()) : 1;
     break;
+  case ISD::AssertSext:
+  case ISD::AssertZext:
+    // Don't allocate a vreg for these nodes.
+    return Reg = SelectExpr(N.getOperand(0));
   case ISD::TAILCALL:
   case ISD::CALL:
     // If this is a call instruction, make sure to prepare ALL of the result