Make sure that the register is in the register class before adding it as a machine op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index f3bc719450f4f830017a0b2d509144c5158dae33..f1000de429f294e8875f5f08777344b3ae7325a1 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -5921,9 +5921,11 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
 
       MachineInstrBuilder MIB(&*II);
 
-      for (unsigned i = 0; SavedRegs[i] != 0; ++i)
+      for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
+        if (!TRC->contains(SavedRegs[i])) continue;
         if (!DefRegs[SavedRegs[i]])
           MIB.addReg(SavedRegs[i], RegState::Implicit | RegState::Define);
+      }
 
       break;
     }