ARM LDM encoding for the mode (ia, ib, da, db) operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 7f073d7c0a1e16075918a82f7a9e65147552a56c..1d3e31015959603d548f921e460d7142a2b63902 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -177,6 +177,8 @@ namespace {
       const { return 0; }
     unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
                                             unsigned Op) const { return 0; }
+    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
+      const {return 0; }
     uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
       const { return 0; }
 

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index f03ef56db8b5a64730981e9ad83b7dde318cbab9..2e3362c609357d7d8b952b1c72ede2515f693db9 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -942,8 +942,10 @@ class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
        asm, cstr, pattern> {
   bits<16> dsts;
   bits<4> Rn;
+  bits<2> amode;
   let Inst{27-25} = 0b100;
-  let Inst{24-22} = 0b010;
+  let Inst{24-23} = amode;
+  let Inst{22}    = 0; // S bit
   let Inst{20}    = 1; // L bit
   let Inst{19-16} = Rn;
   let Inst{15-0}  = dsts;

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index f36a9fde06f70a0e263a6bf9698ee45cdd983f6e..5237a55255eaf0d8f4a16eb90b2973d07d4f5f57 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -456,6 +456,7 @@ def am3offset : Operand<i32>,
 // ldstm_mode := {ia, ib, da, db}
 //
 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
+  string EncoderMethod = "getLdStmModeOpValue";
   let PrintMethod = "printLdStmModeOperand";
 }
 

diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index bd799f233c07373141878b7e239353433f1bd9aa..38f5c7970460cdd35c12522b837a10eab79a33ab 100644 (file)
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -82,6 +82,19 @@ public:
   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
                                SmallVectorImpl<MCFixup> &Fixups) const;
 
+  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
+  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
+                               SmallVectorImpl<MCFixup> &Fixups) const {
+    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
+    switch (Mode) {
+    default: assert(0 && "Unknown addressing sub-mode!");
+    case ARM_AM::da: return 0;
+    case ARM_AM::ia: return 1;
+    case ARM_AM::db: return 2;
+    case ARM_AM::ib: return 3;
+    }
+  }
+
   /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
                                SmallVectorImpl<MCFixup> &Fixups) const;